| FPGAs continue to demonstrate impressive benefits in terms of performance per Watt for a wide range of applications. However, the design time and technical complexities of FPGAs have made application development expensive, particularly as the number of project revisions increases. Consequently, it is important to engage in systematic formulation of applications, performing strategic exploration, performance prediction, and tradeoff analysis before undergoing lengthy development cycles. Unfortunately, almost all existing simulative and analytic models for FPGAs target existing applications to provide detailed, low-level analysis. This document explores methods, challenges, and tradeoffs concerning performance prediction scope and complexity, calibration and verification, applicability to small and large-scale FPGA systems, efficiency, and automation. The RC Amenability Test (RAT) is proposed as a high-level methodology to address these challenges and provide a necessary design evaluation mechanism currently lacking in FPGA application formulation. RAT is comprised of an extensible analytic model for single and multi-FPGA systems harnessing a modeling infrastructure, RC Modeling Language (RCML), to provide a breath of features allowing FPGA designers to more efficiently and automatically explore and evaluate algorithm, platform, and system mapping choices. |
