Process Variation Aware Optimization On Flash-based Storage Systems

In the past two decades,flash memory has gradually replaced hard disk and been widely used in various storage systems,such as databases,computers,mobile devices and so on.Currently,the development of flash memory is to reduce the price by technology scaling,density improvement(increasing bit number per flash cell)or stacking flash cells(3D flash).However,during the manufacturing process,the size and thickness of flash cells become increasingly different,which is called process variation(PV).The intuitive behavior of PV is that the access latency and reliability vary with flash cells.Fast or slow,strong or weak,such kind of flash memory brings opportunities and challenges for the development of embedded systems.From a system optimization perspective,a well-performing flash cell is the target for performance and reliability improvement.However,on the one hand,the process variation of flash memory is unknown;On the other hand,well-performing flash cell number is limited,where improper decision may lead to degradation of performance and reliability.Considering the deep-seated factors of flash memory on performance and reliability,this thesis proposes to exploit process variation to optimize flash embedded systems.Compared with the previous research works,this thesis exploits the process variation of flash memory to make full use of the characteristics of well-performing flash cells,so that performance and reliability can be improved fundamentally.The main contributions of this thesis are as follows:(1)The design on process variation aware write performance improvement.Write performance is the key bottleneck for the overall performance.Through analyzing the relationship between write speed and reliability,many flash blocks have been found that they can support larger write speeds,so that performance can be improved.The first work firstly modulates write speed for flash blocks under process variation according to the error characteristics.Second,it allocates key data to flash block with fast write speed to improve the overall performance.Finally,an implementation is designed on flash controller where the overhead can be negligible.(2)The design on process variation aware retention induced refresh minimization.Refresh operation is one kind of redundant operations,which has bad effects on flash performance and lifetime.However,on the one hand,flash blocks require different refresh frequencies under process variation,while the unified refresh will introduce many unnecessary refresh operations;On the other hand,update operation is conducted by invalidating old flash pages,thus if there are no valid pages in one flash block,the refresh operation on the block can be skipped.The second work first proposes to determine the real retention time of flash blocks,and then get its refresh frequency;Second,according to the update interval of data and the retention time of flash blocks,a match for data and block is proposed to minimize the refresh counts.Finally,an implementation with a small overhead is designed on flash controller.(3)The design on shortening data for low-cost error correction codes(ECC)reliability enhancement.With the development of flash memory,the reliability is decreasing,where ECC with high error correction capability is required for data integrity.However,these ECCs will introduce high overhead,which is not suitable for consumer-level flash memory.This work finds that if the actual data in ECC unit is reduced,the possibility of successful error correction can be significantly improved.Based on the finding,a data shortened scheme is proposed for lifetime improvement.First,this work presents operations for three kinds of mapped flash,including data layout,mapping mechanism and read/write processes.However,shortening data will reduce the available user space.Then,this work proposes three solutions to relax the space reduction: avoiding applying data shortened scheme on strong blocks,avoiding applying data shortened scheme on reliable bit for multiple-bit flash memory,and neglecting the reduced space due to the small data size.This thesis conducted a series of experiments for these works with simulator.The experiment results confirm the efficiencies of these schemes.Among them,the write improvement work can improve the write performance by almost 30%.The refresh minimization work can reduce 50%~90% refresh counts,so that the performance can be improved by 10%~40%,and lifetime can be improved by 160%+.While the reliability enhancement work can achieve another 300%+ data write amount with only 12% space reduction.Overall,by exploiting process variation,the performance and lifetime of flash memory can be improved,which lays the foundation for the development of flash memory,and can also promote the development of the Internet of Things and artificial intelligence with flash embedded devices.