Research On Optimization Method Of Embedded Storage System For New Three-dimensional Flash Memory

NAND flash memory has become the mainstream storage medium for both enterprise high performance computers and embedded systems.However,over the past several decades,the storage primitives that access secondary storage have remained unchanged,forcing NAND flash memory to serve merely as a block device like hard disk drive.Recently,several emerging storage primitives have been presented to explore the potential value of non-volatile memory devices.Although these primitives can significantly boost the access performance by providing virtual to logical address mappings,they still suffer from large RAM footprint to maintain the address mapping table and require further support for update operations.Threedimensional(3D)flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory,including larger capacity,less program disturb,and lower access latency.In contrast to conventional planar flash memory,3D flash memory adopts charge-trapping mechanism.NAND strings punch through multiple stacked layers to form the three-dimensional infrastructure.However,the etching processes for NAND strings are unable to produce perfectly vertical features,ESP espcially on the scale of 20 nanometers or less.The process variation will cause uneven distribution of electrons,which poses threat to the integrity of data stored in flash.This thesis presents ESP to optimize Emerging Storage Primitives with virtualization for flash memory storage systems.We propose two optimization strategies,virtual duplication and mapping prefetching to solve the critical issues in existing emerging storage primitives.The objective is to reduce unnecessary flash memory accesses and keep RAM footprint of address mapping table well under control.We have evaluated ESP on an embedded development platform.Experimental results show that ESP can significantly improve the write/read performance and reduce over 30% of garbage collection operations.This thesis also presents P-Alloc,a process-variation tolerant reliability management scheme for 3D charge-trapping flash memory.P-Alloc offers both hardware and software support to allocate data to the 3D flash in the presence of process variation.P-Alloc predicts the state of blocks and tries to assign critical data to more reliable blocks.A hardware-based voltage threshold compensation scheme is also proposed to further reduce the faults.We demonstrate the viability of the proposed scheme using a variety of realistic workloads.Our extensive evaluations show that,P-Alloc significantly enhances the reliability and reduces the access latency compared to the baseline scheme.