GNSS Acquisition Algorithm And Circuits

In recent years,smart mobile phones,smart watches,sports bracelets and other mobile devices are gradually emerging,where the positioning and navigation components are the most important sources of power consumption.Since the acquisition engine is the main energy-consuming unit in a GNSS receiver,reducing the acquisition power consumption is particularly important for enhancing the GNSS receiver's endurance.This dissertation studies the low-power GNSS acquisition engine from both the algorithm and circuit aspects.(1)Algorithm.Aiming at the problem that the traditional GNSS acquisition algorithm does not pay enough attention to the acquisition energy cost,this dissertation first proposes the metric of acquisition energy efficiency-the acquisition mean computation overhead(AMCO).Then,in view of the problem of low acquisition efficiency of traditional GNSS weak signal acquisition algorithm,a multi-peak dual-dwell(MP / DD)algorithm is proposed,which is to select the peak and sub-peaks as the candidate acquisition results in the first dwell and the second detection adopts the candidate amount whose signal to noise ratio is improved.The simulation results show that the signal detection probability of proposed algorithm is 70% when the signal to noise ratio is 23dB?Hz,which is increased by 52% compared to DD/MAX.And its AMCO is only 30% of the DD/MAX algorithm.At last,a weak signal acquisition algorithm(DD/CEI)based on convolution neural network(CNN)is proposed.The detection amount envelope is detected by convolutional neural network,and the signal parameter range is reduced to 1/1023,and then the peak is detected by high SNR signal after a long time integration.The results show that the DD/CEI algorithm can improve the signal acquisition sensitivity by 2dB compared with the MAX/TC algorithm under the same computational load.With the same sensitivity,the AMCO of the DD/CEI algorithm is only 1/5 of the MAX/TC algorithm.A double-dwell hybrid-grained acquisition engine is designed which adapts to both MP/DD and DD/CEI algorithm.The coarse-grained acuqisition module and the fine-grained acquisition module are scheduled in pipeline under the control of software,whose speed is improved compared to the traditional double-dwell algorithm.(2)Circuit.Firstly,power consumption of the acquisition engine is decomposed and the goal of power optimization is determined in matched filter and coherent integration memory.Secondly,aiming at the high power consumption of summation in matched filter,a matched filter based on delay chain is proposed where each delay chain reprensents 1-bit addition and multi-bit summation completes in digital domain.Replica oscillator and 2-point calibration method compensates for deviation caused by process,voltage and temperature.Simulation results show that the loss of signal-to-noise ratio of the delay-chain matched filter can be controlled within 1.5dB compared with the accurate digital filter.Thirdly,since traditional separated calculation and storage cause high power consumption,this dissertation proposes in-memory coherent integration where adders are embedded in static memory(SRAM).Three operations as reading memory,adding and writing memory are completed in each cycle.Simulation results show that the power consumption of in-memory coherent integration is only 30.4% of the traditional scheme.GNSS acquisition algorithms and key circuit technologies are verified in two phases.(1)Firstly,algorithm/architecuters are verificated based on SMIC 40 nm CMOS process.The double-dwell hybridgrained acquisition engine is integrated in digital low power GNSS baseband chip.The chip test results show that the signal acquisition sensitivity of the acquisition engine is-148 dBm which is equal to industry-leading products.Acquisition probability of test results is 1% lower than simulation.The power consumption is only 4.1mW,which is about 1/7 of the commercial GNSS acquisition engine implemented by the same process;(2)Secondly,key circuit technologies are verificated based on SMIC 28 nm CMOS process.The fully customized chip use delay-addition,in-memory integration and voltage stacking.The chip test results show that channel circuits works stablely at 0.55 V when the chip operating voltage is 1.1V.The power consumption is as low as 0.46 mW,and its energy efficiency inceases by 4.68 times,5.46 times and 6.3 times respectively compared with the all-digital low-voltage acquisition engine chip,the switching current source array chip and the switched-capacitor array chip.