Acquisition Algorithm Research And Fpga Implementation Of High Sensitivity Gnss Receiver

With the acceleration of the process of the construction of China’s Beidou system, the advance of the Russian GLONASS and U.S. GPS modernization, the Global Navigation Satellite System GNSS applications are increasingly widely. The integrated navigation will gradually replace the single-frequency point navigation. It combines the processing mechanism of the GPS, GLONASS and Beidou satellite. It can provide users with a more precise of navigation and positioning. But, the receiver needs a better algorithm support to improve the weak signal sensitivity and successfully intercepted high dynamic signal.In this paper, the GNSS receiver capture algorithm are studied, and mainly proposed the improved mothod for improving the sensitivity of weak signal. The main contents are as follows:First, it introduced an overview of GNSS system and analysis of the characteristics of the satellite signal. The communication theories of receiver are described deeply. Besides, it designed the all parts of the GNSS receiver.Secondly, a time-frequency two-dimensional search algorithm-capture algorithm of "multi matched filter+FFT" are proposed.The capture performance and validation strategy are researched and the external interface of capture part are analyzed in engineering implementation.Again, it introduced methods to improve the receiver capture sensitivity, that is bit transition detection and large parallel correlation. It maked improvements for down-sampling filter and the non-correlation accumulation of the existing algorithms. It is respectively replaced with CIC down-sampling filter and differential coherent accumulation. So, the sensitivity is improved by about2-3dB. Different kinds of interference seriously affect the capture of signal. So this article specifically studied Repeater Jamming. The superiority of these algorithms has been well verified in the theoretical simulation and practical testing.Finally, the article described the FPGA realization of the capture module of carrier NCO, code NCO and the time-frequency two-dimensional research implementation. In addition, for the limited resources, the paper also raised a bit compression method to save resources. This design will compress from9bit to7bit in RAM unit. It saved245KB for RAM resources.