Research On Evolvable Self-adaptive Systems Based On Digital Circuit

With the rapid development of the electronic technology,the people have higher and higher requirements for the functional diversity,intelligent behavior and system stability of electronic products.Self-adaptive system has become an inevitable trend in this field.The essence of the Evolvable Hardware(EHW)is that the programmable device,drived by the biological heuristic algorithm,can modify its structure and behavior in real time to adapt to the change.The self-organizing,self-adaptive and self-healing characteristics of EHW advance the research of self-adaptive systems.As a result,the dissertation regards self-adaptive system based on EHW as the research object,simulates the implementation on Field Programmable Gata Array(FPGA),and conducts a series of researches,including evolutionary design approach of digital circuit,module design method for scalability problem,self-reconfiguration and redundant fault tolerance method based on EHW and the construction of self-adaptive system platform.Evolutionary design approach is the means to realize self-reconfiguration of EHW and drives the development of self-adaptive system.The dissertation analyse the advantage and disadvantage of function-level Virtual Reconfiguration(VRC)and LUT-level VRC,and proposes a improved function-level VRC to relieve the limitation of the traditional cascade-level VRC circuit architecture by combining with Cartesian Genetic Programming(CGP)encoding,so as to increase the circuit diversity generated by evolution.The existence of redundant nodes in CGP encoding is beneficial to neutral effect.In order to promote the utilization rate of the redundant nodes,we integrate MEP encoding idea,and then propose a Two Stage mutation ES(TMES)based on(1+?)ES to improve the probability that feasible solution be detected in iteration,which use different mutation probability based on the different charateristics of connection of nodes chromosome and output chromosome.In order to further improve the evolution efficiency,we intoduce interactive strategy to generate an Interactive TMES(ITMES),which produces excellent gene segments through injecting excellect individuals to cross in skipped generation.Finally,we take the 2-bit multiplier,3-bit full adder and 3-bit multiplier as the experiment,the results show the effectiveness of the improved function VRC structure,and ITMES is best,and TMES is better than(1+?)ES in evolution efficiency.But TMES and(1+?)ES have more diversity than ITMES,because ITMES leads to the fast convergence of the individual by accelerating the evolution speed and simplify the circuit structure.The scalability problem is the main bottleneck of the development of the evolvable hardware.At present,many different methods were proposed to solve the problem,such as function design,decomposition mechanism,modularization design and fitness evaluation.We compare these methods and choose modularization design as the research method,analyze the ECGP method's features and shortage,and then proposed a modularization design based on development mechanism.Finally,we take 4-bit full adder as the experiment.According to the strong correlation between the module selection and the target circuit,we select module function and granularity by the user interactive and use respectively by type ? gate cells,type? module cells and ? + ? cells based on the development mechanism.The results show that the type ? +? has obvious advantages in the evolutionary success rate,diversity and the evolution efficiency.The scheme has improvement in evolution scale and evolution efficiency.Fault tolerance is the means to realize the self-healing of EHW.At.first,we propose a three-module heterogeneous redundancy fault-tolerant architecture based on TMES and ITMES by analyse the advantages and disadvantages on the traditional redundant fault-tolerant,reconfigurable fault-tolerant and compensation fault tolerance to realize dynamic self-repair in real-time to the soft error and hard error of the circuit.The higher heterogeneous produce the stronger ability to deal with error.In order to generate higher heterogeneous individuals,we construct a heterogeneous evalution module based on function heterogeneous and position heterogeneous to solve convergence problem of successful individual generated by ITMES.The ITMES algorithm evaluate the success individual by combining the heterogeneous evalution module and artificial interactive evaluation.Due to better heterogeneity and evolution efficiency,the direct insertion interaction strategy is selected by comparing with intergenerational cross interaction to increase the individual's reliability in the successful individual pool.Then,we propose a multi-objective algorithm with more heterogeneous between individuals and less active nodes.That is constrainted by heterogeneous and power consumption to filter the successful individual pool to improve the quality and the performance of the fault-tolerant architecture.Finally,we take the three-multiplier as experience to prove the feasibility of the scheme.Based on the above research about evolvable hardware,this dissertation puts forward a kind of self-adaptive system architecture in order to work in changing enviroment,which is composed of execution unit,adaptive engine and the monitor mechanism,and then state the realization scheme of the architecture on the FPGA Soc platform.We give the reason why we choose the function VRC to realize fault tolerant architecture based on three-module redundancy with different structure by comparing VRC and Dynamic Partial Reconfiguration(DPR).Finally,the validity of the self-adaptive platform is verified by the example of 3-bit multiplier example.