Research On Key Technologies Of Analog Front-end Receiver Of Monolithic Linear Mode LADAR

Since the laser was invented,laser detection equipment has been a research hotspot.From the initial laser range finder,laser seeker,to the mature scanning LADAR and the developing three-dimensional laser imaging,laser detection equipment has evolved from single-channel semi-active detection to multi-line/large-area active detection,which is accompanied by advances in semiconductor integrated technology and optoelectronic devices.The goal of this dissertation is to realize the analog front-end readout circuit of linear mode LADAR by means of integrated circuit technology to reduce the volume and power consumption of the receiving module,and then use the three-dimensional packaging technology to finally realize a monolithic integrated LADAR detection system.Based on the deep analysis of the working principle,this dissertation studies the key technologies of the analog front-end receiver of the linear mode LADAR.According to the different application scenarios,this dissertation implementes a single-channel analog front-end receiver for on-board scanning LADAR,and a dedicated readout integrated circuit(ROIC)for matrix four-quadrant LADAR which is applied to search and trail target in a wide range,and at last,a 100MS/s 10-bit high-speed successive approximation analog-to-digital converter(SAR ADC)is implemented to acquire the output data of the linear mode LADAR.The single-channel front-end receiver of the scanning LADAR can realize a laser pulse time-of-flight(TOF)detection,and the double threshold timing discrimination is used to improve the detection accuracy.Impletented in the SMIC 0.18?m CMOS process,its effective area is 0.85 ×0.67mm2.The receiver uses a regulated cascode amplifier(RGC)with additional feedback as the input stage to effectively increase the bandwidth.And a analog selector is utilized to adjust the transimpedance gain and widen the dynamic range.Finally,two high-speed low-delay-spread comparators with different thresholds are used to obtain the leading edge of the laser echo pulse and the timing difference of the discriminant signal,which is used to correct the walk error.The test results show that a bandwidth of 350MHz,four gain modes of 54dB?/66dB?/80dB?/94dB?,a linear dynamic range of 66dB can be realized.Meanwhile,two low-delay-spread timing comparators are utilized to acquire a maximum timing difference of 480ps to effectively correct the walk error of the TOF,so that the detection accuracy of the receiver reaches 10cm.In order to meet the requirements of fast searching and tracking in a large field of view,a matrix four-quadrant LADAR is proposed.This LADAR is based on a 32×32 avalanche photodiode(APD)array,and its dedicated ROIC is implemanted in SMIC 0.18?m CMOS technology to achieve a total area of?13× 13mm2.The ROIC completes 32×32 unit readout circuits with the proposed current-mirror gain-adjustable transimpedance amplifier(TIA)which utilizes a current mirror with a level shifter to effectively reduce the input resistance and extend the linear dynamic range.Since only 2×2 pixels are illuminated for each detection,the ROIC automatically transmits the voltage pulses of the active cells to the corresponding peak detection hold(PDSH)circuit through the 256:1 multi-channel analog selector,and then the high-speed PDSH circuit with variable current source accurately transmits the echo peak to the post-stage circuit.At the same time,a high-speed offset comparator in the unit can automatically detect the effective pixels and output the position coordinates of the irradiated pixels to the external control system through the effective pixels retrieval circuit.The peak information obtained by the four PDSH circuits can be used to caculate the offset of the echo spot in the small quadrant matrix,and the position of the small matrix in the large array can also be obtained by using the effective pixels retrieval circuit.The measurements show that the goals of the unit transimpedance gain of 106dB?,the bandwidth of 50MHz,the minimum detectable current of 500nA,the linear dynamic range of 80dB,and the maximum swing of more than 1V are all ahieved.When a 70ns pulse width pulse is detected,the overshoot error of the proposed PDSH circuit is less than 3mV,which meets the input accuracy requirement of the post-ADC.In order to improve the accuracy of the matrix four-quadrant LADAR,a high-speed ADC can be used to obtain the amplitude of the voltage pusles generated by these four pixels,which can accurately calculate the offset of the echo spot.And in conjunction with the effective pixels retrieval circuit,the orientation and distance of the target can be quickly obtained,thus greatly improving the searching efficiency.To this end,this dissertation implements a 10-bit 100MS/s high-speed low-power SAR ADC.A new high-linearity low-power SAR switching capacitor procedure is proposed based on the split capacitor switching procedure.Compared to the VcM-based switching procedure,the proposed procedure reduces the quantity of the unit capacitor in the digital-to-analog converter(DAC)by switching the lowest bit capacitor,thereby reducing the power consumption.Moreover,compared to the traditional switching procedure,the decision of the first two codes(MSB and 2nd-MSB)of the proposed procedure just depends on the VDD/GND,which avoids the slow charging efficiency of Vcm voltage on the large capacitors.For a 10-bit SAR ADC,the proposed switching capacitor procedure just requires 28 unit capacitors,and the power consumption is only 47.7C·Vref2.Compared with the traditional switching capacitor procedure,the power consumption of the proposed switching capacitor procedure is reduced by 96.5%.Using a two-stage structure of preamplifier + latched,the offset voltage,kickback noise,and power consumption of the high-speed dynamic comparator are effectively reduced.In addition,through an asynchronous SAR control logic,the SAR control logic delay is reduced,the conversion rate is increased,and the introduction of the off-chip high frequency clock is also avoided.Implemented in the SMIC 0.18?m CMOS process,the effective area is 0.48×0.45mm2.At 100MS/s sampling rate and 9.86MHz single tone input,the proposed ADC achieves an SNDR of 52.35dB and an SFDR of 63.49dB,leading to an effective number of 8.24bits,which meets the reqiurements of the matrix four-quadrant LADAR data acquisition.