Design Of Interface Circuit For Apds Work In Linear Mode

Avalanche photodiode(APD) works in linear mode has advantages of high photon detection efficiency, low power consumption and short detection interval, which has been widely applicated in kinds of faint light detection and imaging systems. During detection process, APD receives faint light signal and outputs current signal, interface circuit detects this signal and outputs the detection result to the next process circuit. The amplitude of the current pulse output by APD works in linear mode is ultra low and the current pulse width is extremely short which is difficult to be detected. So it is of vital importance to design a interface circuit with proper performance. While with the detection and imaging system tend to extend its array size, the constraints of power consumption and area of the interface circuit become more and more strict, which leads more challenge to design a high performance current detecting interface circuit.This thesis accomplished a current detection interface circuit with tiny area and low power consumption which is suitable for large array application according to the characteristic of APD works in linear mode and the needs of the project. The former amplify of the interface circuit is a transimpedance amplify with regulated cascode input stage, which has features of high bandwidth and low power consumption. The thesis use MOS resistances to replace part of the polysilicon resistances and saved lots of area. For the application of MOS resistances would lead the output static voltage of the transimpedance amplify occur large drift, the thesis set a differential input voltage amplifier with high common mode rejection ratio to depress this drift. The voltage amplifier also has been adjusted and optimized in order to save area in condition of keeping its performance.The interface circuit is taped-out using TSMC 0.35?m CMOS process. The post simulation results show that the minimum current the circuit could detect is 1.17?A under 29?m×79?m layout area. On account of many constraints in test, the interface circuit used test circuit to test its performance. The result of the test indicates that the interface circuit could detect a valid current pulse correctly and through the comparasion between the results of test and post simulation, it could predict that the minimum current the the chip circuit could detect is 1.8?A under 0.25mA static power consumption. This thesis also summarized the whole design process and put forward related advise to go on to optimize the circuit.