Research On Charge Sharing Effect Induced Single Event Upset Effect In CMOS Integrate Circuits

China's aerospace science and technology has made rapid development in recent years,along with urgent research needs in advanced technology of integrated circuit radiation reinforcement for aircraft.When the size of anti-radiation integrated circuit scales down to nanometer,the integrated circuit chip will correspondingly have increased number of transistors,higher clock frequency,decreased working voltage and lower node capacitance,where soft errors become the main reason of integrated circuit failure in spacecraft,therefore presenting new challenges for single event upset study in terms of charge sharing.The reduction of device size and spacing in nanometer technology could make the trajectory of single heavy ion cover multiple devices at the same time,resulting in simultaneously charge collection by these devices.The multi-device charge collection phenomenon caused by charge sharing effect has induced more complex circuit response and more severe reliability problems in nanometer integrated circuit.Therefore,charge sharing effect mechanism and experimental characterization of nanometer integrated circuit have become the research focus in integrated circuit radiation effects.On the other hand,more serious charge sharing will lead to the failure of the reinforcement method for single node,thus the inhibition of charge sharing effect has turned into an important measure to avoid circuit soft error.How to design an effective reinforcement technique to alleviate the influence of charge sharing has also become an important issue.In addition,layout structure,outer particle,doping process,power supply voltage,body-bias and other factors could vary with the changes of practical application environment,which will greatly influence the charge sharing and the reliability of integrated circuits.Therefore,in-depth study of the charge sharing effect on nanometer integrated circuits soft error could provide assistance to resolve important research problems of integrated circuit radiation,and guide the design of nanometer anti-radiation reinforced integrated circuit.In this thesis,the mechanism of charge sharing effect,measurement approach and reinforcement technology have been specifically discussed for the technology of nano complementary metal oxide semiconductor(CMOS).The main achievements are listed as follows:A DICE-based test structure has been proposed to measure the influence of charge sharing.This structure can fully use the property of DICE latch and the features of sensitive nodes on simultaneously charge collection.The numerical simulation of three-dimensional computer-aided design(TCAD)has proved the feasibility of this test structure.In addition,a test chip is fabricated by the commercial 65 nm bulk CMOS process to verify our proposed test structure.Heavy-ion experimental results has shown the efficiency of this test structure on obtaining the influence of charge sharing.Based on the measurement results of charge sharing scope,this thesis has intensively investigated the influence of charge sharing on SEU trigger unit.TCAD numerical simulation has used to analyze the charge sharing effect on the trigger sensitive area.Furthermore,according to different inpu t data,the variation of the sensitive area has been examined to reveal the mechanism of trigger data dependence.A novel reinforced latch for resisting the SEU is also proposed in the thesis,by exploiting the combination of the circuit structure and layo ut placement to enhance the multiple nodes upset resistance.This latch consists of a normal D latch and a typical DICE latch.Different from the TMR latch,the proposed latch design can eliminate the charge collection on two transistors.HSPICE simulation results show that there are only four sensitive transistors pairs in this latch.Compared to typical DICE and DMR latch,the sensitive transistor pairs can be significantly reduced in our latch.In addition,these sensitive transistor pairs can be separat ed from each other as much as possible by adjusting the layout placement.Charge collection on the sensitive transistor pairs is almost eliminated in our proposed latch.Based on the traditional 6T-SRAM cell,a novel layout placement structure to mitigate the multi-bit upset has been designed and presented in the thesis.The TCAD numerical simulation is used to analyze the multiple bit upset(MBU)mitigation mechanism and reinforcement performance.Compared to the traditional 6T-SRAM cell layout structure,our proposed layout can effectively improve the performance of anti-MBU in typical 6T-SRAM with little area cost and power consumption.