Researchs On Single-Event Upset Mechanisms And Hardening Techniques For 65nm DICE Storage Cell

There are large numbers ofenergicparticles in the space. These particles threatened the spacecraft's work. While a particle strikes the semiconductor device of spacecraft a variety of effects appeared. These effects threatened the reliability of the semiconductor device. While the particle strikes the combinational circuit, the single event transient(SET) occurred. While the particle strikes the sequential Circuits, the single event upset(SEU) occurred. The DICE can weaken the SEU because of the dual redundant structure. With the technology scaling down, the reliability of the DICE decreased. This paper researched the single event sensitivity and upset mechanism of the 65 nm DICE memory cell and hardened it by several methods.The main work in this papper is as follows:First, this papper analysed the circuit features and the single event upset mechanism. Athree dimensional(3D) device/circuit mixed modelis constructed using technology computer aided design(TCAD), which is used to investigate the sensitivity between the sensitive node pairs in DICE cell and the effect of distance between the sensitive pair on upset LET threshold in 65 nm DICE.Second, this papper investigated the affect of supplyvoltage and well contact on the DICE sensitivity. The research shows that the decrease of supply voltage and the width of well contact increased the sensitivity of DICE. The influence of supply voltage on NMOS is more visible than on PMOS. When the width of well contact decreases, the distance between transistor and well contact increased and the area of well contact decreased. Hence, the decrease of well contact width increased the sensitivity of DICE in these aspects.Third, this papper researched the sensitivity of DICE in 3-well and SOI technology.The stability of PMOS in 3-well technology is more obvious than that in 2-well technology, but the sensitivity of NMOS in 3-well technology is more obvious than that in 2-well technology. In the SOI technology, the stability of DICE is more obvious than that in bulk silicon technology. However, the performance of the DICE in SOI technology is very poor because the channel current is very small.Last, this papper combined multi-cell height technology, layout interleaving technology and N+ deep well new technology, designed several layout of the DICE and simulated the LET upset threshold of the sensitive node pairs by the TCAD.