Analysis And Design Of High Speed LDO Driving SRAM

The low dropout linear regulator is one of the power management chips.It has a wide range of applications in electronic devices,such as memory chips and solid state drives,as well as DAC and ADC chips,PLL and so on.It also has a wide range of commercial and industrial uses,such as consumer electronics,wireless communication equipment,testing instruments,and small and medium-sized medical devices.Different LDO linear regulators have different performance advantages,such as high precision,high power supply voltage rejection ratio,low noise and excellent transient response performance.Therefore,LDO plays an important role in the IC industry.Static random access memory(SRAM)has the characteristics of logical process compatibility,its high speed read and write function and low power consumption,so it has been widely used in the field of electronic information and communication.In static random access memory,memory cell and some sensitive components are very sensitive to power supply and need to meet its high-speed read and write function.Therefore,high-speed transient response performance is required,which requires high power modules inside the memory chip.This thesis presents a high-speed LDO linear regulator based on Intel 22 nm Fin FET CMOS technology.Its driving capability is 150 m A,and is used in SRAM power system.The LDO linear regulator consists of an error amplifier(slow loop),a power adjustment tube,a turn over voltage follower(fast loop)and a self calibration module.The slow loop produces a stable output voltage;the voltage signal passes through the loop of the replication loop and then enters the fast loop,and the fast loop routing follower voltage follower and power tube have the characteristics of large slew rate and large bandwidth.When the output of the LDO linear regulator generates a jump of load current,the transient response of the whole system is fed back in the fast loop to regulate the voltage.Because the flip voltage follower has shorter feedback path and larger bandwidth and slew rate current,this special structure can bring high-speed transient response,so as to achieve the high speed response function of LDO linear regulator to meet the stable power supply of static RAM.The LDO also has a self calibration module to ensure that the output voltage is more accurate.In this paper,the Cadence software is used to analyze the circuit and layout of each module of the circuit and the top level of the LDO linear regulator,and the simulation analysis is made before and after layout.The simulation results show that under the 1.24 V supply voltage,the output voltage of the high speed LDO linear regulator is 1.054 V,and the temperature coefficient in the range of-40~125degrees Celsius is 32.37ppm/?.At low frequencies,the PSRR of the system is-57 d B.Its power consumption is 6.86 m A.In the compromise design process,in order to meet the high speed transient response performance,the load regulation rate and linear regulatuon rate are sacrificed,the load regulation rate is 0.095V/m A,and the linear regulation rate is 0.04V/V.When the output load current changes from 0 to 150 m A,the mutation time is 1ns,the output overshoot voltage is 28.2m V,the overshoot recovery time is 23 ns,the output overshoot voltage is 18.8m V,the overshoot recovery time is 34.5ns,the system has the performance of high speed transient response,and can drive the read and write work of the static random access memory at high speed.