Design And Implementation Of A Novel Multiple Bit Upset Hardening SRAM On 65nm Process

As an important part of CPU and SoC, SRAM is widely used in areo-space crafts. Radiation effect in space environment is the major reason for areo-space crafts failure. SRAM is more prone to soft error events due to lower critical charge. It is indispensable radiation hardened SRAM.The rapid development of space industry brings out a higher request on the radiation hardened integrated circuits. It’s the trend to use less dimension for higher performance.With feature size and supply voltage scaling down and the increasing of operating frequencies, SRAM faces more and more difficult challenges in radiation hardening. Firstly, with the scaling down of supply voltage, the critical charge of integrated circuits decreasing and making SRAM cell more susceptible to upset. Secondly, with the number of transistors integrated on a chip is increasing, radiation–induced multi-bit upsets(MBU) on SRAM increasing, MBU led traditional radiation-harden SRAM cell are facing failure. In addition, with the increasing of operating frequencies, the soft error rate induced by SET increasing.It is indispensable radiation hardened combinational logic in SRAM.(1)For traditional radiation- harden SRAM cell are susceptible to MBU. We propose a novel MBU hardened SRAM cell. The sensitive node in SRAM cell are protect by isolation transistor, and a novel layout has been proposed to reduce the MBU vulnerability. The simulation result confirms its well performance for MBU. Further more, we optimize the SRAM cell based on static noise margin and radiation hardening performance.(2)We propose radiation- harden methods for combinational logic in SRAM. We propose a radiation hardened sense amplifier based on source- isolation technique. TCAD simulation result showed that source- isolation technique in sense amplifier can significantily reduce SET pulse width. We design etcaeeras combinational logic in SRAM based on Muller C structure, simulation result showed the structure ca n reduce SET pulse width.(3)We design a radiation hardened SRAM based on CMOS technology. The design of a 512x36 SRAM with full custom method based on 65 nm CMOS technology is described. We complete the whole flow including circuit design and layout design.