| The Large Hadron Collider(LHC)is the world’s largest and most powerful particle accelerator.The LHC provides unique opportunities to search for new physics and to answer most fundamental questions in particle physics,such as the origin of mass,the matter-antimatter asymmetry,extra spatial dimensions,and the properties of dark matter.After upgrade in the next decade,the LHC,with the new name of the High-Luminosity Large Hadron Collider(HL-LHC),is expected to further increase the integrated luminosity by a factor of 10 beyond the current LHC’s design value.A Toroidal LHC Apparatus(ATLAS)is one of the two general-purpose detectors at the LHC and is specially designed to maximize the potential to uncover signs of new physics at the LHC.The HL-LHC requires major upgrades of the ATLAS detector in order to maintain or improve its current performance under new challenging operating conditions.Monitored Drift Tube(MDT)chambers,as one key sub detector in ATLAS,are used for precise tracking in the ATLAS muon spectrometer.Upgrade of the LHC results in significant increase of background hits,with a required trigger precsion beyond the capability of the current muon spectrometer.To handle a large number of background hits and low momentum muon tracks,in Phase II upgrade ATLAS plans to include data of the MDT chambers into the first trigger level to provide additional rejections of fake muons and to improve the muon momentum resolution by sharpening the trigger turn-on curve.The Time-to-Digital Converter(TDC)ASIC is a key component in the new trigger and readout architecture.It is responsible for the time digitization of raw tube signals with reduced readout latency,which is the basis for all following trigger and readout processing.To cope with the requirement of ATLAS Phase II upgrade,the TDC ASIC needs to be redesigned,featuring low readout latency,low power consumption,compatibility of both the triggerless and trigger readout modes,and flexible data interface.This dissertation focuses on the research of a fully-featured TDC ASIC for the Phase Ⅱ upgrade of the MDT electronics.The TDC ASIC was fabricated in the 130 nm CMOS technology.Test results indicated that the design meets all requirements of the MDT font-end electronic for the Phase Ⅱ upgrade.This dissertation is organized as follows:In Chapter One,the LHC,the ATLAS experiment and the ATLAS MDT system are introduced.The present architecture of the front-end electronics for the MDT detector is also presented.The current MDT front-end electronics are required to be redesigned to achieve a better trigger precision and efficiency,in which one key component is the TDC ASIC.In Chapter Two,mainstream TDC design techniques are introduced.To cope with a variety of application scenarios,a number of conversion methods have been proposed.In this chapter,these methods are discussed including their principles and performances.And the cases that these methods are implemented in FPGA or ASIC are also introduced.In Chapter Three,the design scheme of the MDT TDC ASIC is presented according to the Phase II upgrade requirements of the MDT font-end electronics.A multi-phase clock interpolation technique is employed for the fine time digitization.The design and optimization of a key circuit block(clock phase sampling register)is also presented.In Chapter Four,the readout logic of the MDT TDC ASIC is described.Both the low latency triggerless and based on channel CAM(Content Addressable Memory)trigger readout modes for the TDC are discussed in detail.Designs of multiple interfaces such as configuration interface,control interface and data interface for the TDC are also presented.In Chapter Five,the layout and package of this TDC ASIC is illustrated.A TDC ASIC was successfully desgined based on a CMOS 130 nm technology,integrating 24 double edge measurement channels.An evaluation system for this ASIC is also described.Performance test results indicate that this ASIC meets the design goal.A bin size of 781.25 ps with a variation of less than ±40 ps is achieved,while the time resolution is 273 ps RMS(a best result is 64 ps RMS).The overall power consumption is 250 mW.The package loss rate is less than 0.1%at a readout latency of 450 ns.In addition,a further interpolation using multi channels is implemented,resulting in enhancement of this TDC,with the bin size reduced to 195 ps(± 20 ps variations)and a time precision of 68 ps RMS(a best result is 43 ps RMS).Finally,this dissertation is concluded in the last chapter and the plans for future research such as the TMR are presented. |
