| ATLAS liquid argon (LAr) calorimeter which is used to measure the energies carried by the particles is one of the important components of the ATLAS detector. The front-end (FE) readout system is on the detector area. It’s used to sample and transmit the signal data to the back-end (BE) counting room for analyses and processing. In the LHC experiments, the whole FE system is in a harsh radiation environment, thus all components must meet the radiation-tolerant requirements. Since commercial chips usually cannot meet the requirements, series of radiation-tolerant Application Specific Integrated Circuits (ASICs) have been designed for these experiments. Along with the upgrades of LHC, the energy, the luminosity as well as the granularity will be increased significantly. This will lead to the requirements of high-speed and low-latency optical links.Based on a radiation-tolerant commercial0.25-μm Silicon on Sapphire (SOS) CMOS process, this paper describes several optical data transmission ASICs which have been designed for the ATLAS LAr calorimeter readout Phase-I upgrade, including Vertical Cavity Surface Emitting Laser (VCSEL) drivers (LOCldx) and a dual-channel data transmittion (LOCx2). All the ASICs feature high-speed, low-power, low-latency and small-form-factor performance. These designs are verified achieving the design goal by the laboratory and radiation test results.Two8-Gbps-per-channel VCSEL driver ASICs has been presented in this paper, including a single-channel driver LOCldl and a dual-channel driver LOCld2. Both ASICs use several techniques to extend the bandwidth, such as multiple driving stages, active inductor shunt peaking and higher power supply (3.3V instead of2.5V). Constant current source which is insensitive to the radiation-induced threshold voltage shift has been used as the reference of the bias current and the modulation current. Several DACs and an I2C slave module which is protected with Triple Modular Redundancy (TMR) have been added to program the bias current, the modulation current and the peaking strength. Therefore, LOCld1/LOCld2can easily adapt to different VCSELs and working environment.The laboratory tests show that LOCld1/LOCW2can amplify a low-swing Current Mode Logic (CML) signal (Differetial200mV (peak-to-peak) minimum) to drive the VCSEL at8Gbps data rate. They also can pass the Bit Error Rate (BER) test at the10-12level at10Gbps. The measured peak-to-peak total jitter is less than30ps, and the total power consumption is about200mW per channel. If we input a signal with larger amplitude, as300mV differential, we will see a better eye diagram at10Gbps. The neutron and X-ray tests show that LOCld1meet the ATLAS radiation-tolerant requirements. Since LOCld2has the same architecture of the driver with LOCld1, we assume it has a similar performance after irradiation. The measured performance of LOCldx is very good; some features are comparable with the GBLD which is designed by CERN; some features are even better than the GBLD. Laboratories such as BNL, UMN and IPAS, are willing to use LOCldx chips.This paper also presents a dedicated two-channel5.12-Gbps-per-channel serializer ASIC, named LOCx2. LOCx2consists of a two-channel8:1serializer module (LOCs2), two encoder modules (LOCic), one LC phase locked loop (LC-PLL), one I2C slave module and several CML drivers. These building blocks have been designed and tested. LC-PLL as a key component is emphasized. A RC filter is used in VCO to reduce noise contribution from its bias circuit. The measured random jitter, the deterministic jitter and the total jitters of the LC-PLL is1.5ps (root-mean-square),8ps (peak-peak) and25ps (peak-peak), respectively, while the measured frequency is about10%higher than simulation, due to the process variation which is larger than we expect. Therefore, a wide-band LC-PLL with a tuning range of40%has been designed and integrated in LOCx2. The power consumption is about55mW. The phase noise of the LC-PLL is-115dBc/Hz, which is5dBc/Hz smaller than the one before optimization.Based on the test results of each module in LOCx2, we can estimate that the total latency is less than30ns, the total power consumption is about0.85W, and the total data transmission jitter is less than55ps. If the Kintex-7FPGA is used to implement the deserializer and a decoder, the total latency of the whole optical link (transmitter LOCx2and the receiver) excluding the time passing through the optical fiber is no more than58ns, which is much smaller than the150-ns latency budget of each LTDB. Features of LOCx2are comparable with or even better than other radiation-tolerant high-speed data transmitters, such as GLink, GOL and GBT. LOCx2has been integrated and fabricated in December2014; tests will begin in April2015. |
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