The Study And Design Of Time To Digital Conversion System For TRPC In The ATLAS Muon Spectrometer Phase-? Upgrade

ATLAS is one of the seven particle detectors constructed at the Large Hadron Collider(LHC),a particle accelerator at European Organization for Nuclear Research(CERN)in Switzerland.This detector is designed to detect and investigate many types of physics,like measurement of the Higgs boson,the properties of the top quark,the possible clues of CP violation in ? decay,and so on.In Jul.2012,the Higgas boson was detected by ATLAS and CMS separately,which is great encouragement to the physics researcher.In order to improve the detectable ability of ATLAS,the ATLAS collaboration has decided to do the hardware upgrade of ATLAS during the shutdown time of LHC in the following years.The upgrade project was named ATLAS Phase-I and ATLAS Phase-II.Based on the introduction of the ATLAS Muon Spectrometer Phase-I upgrade,we discuss the following issues in the thesis.Firstly,we describe the requirement of time to digital conversion system for the tRPC detector in the ATLAS Muon Spectrometer Phase-I upgrade.Then,we introduce the latency simulation of HPTDC by using its Verilog simulation code provided by CERN micro-electronics group.And find out the reasonable parameter setting of HPTDC from the latency simulation which can make the latency of HPTDC to achieve the time requirement of tRPC readout.Next,we make a detailed introduction of HPTDC and GOL test board.Based on this test board,we finish the latency test of HPTDC according to its simulation,and the function test of HPTDC and GOL chips.All of these test results can be the experimental evidence for the design of time to digital conversion system.Finally,we introduce the detailed design of time to digital conversion system and present the preliminary test results of this system.This thesis is arranged as follows.In chapter 1,we illustrate the construct of LHC and ATLAS,and give a brief overview of the ATLAS Muon Spectrometer Phase-I upgrade.Then,we introduce the research background and contents of this thesis.This is the study and design of time to digital conversion system which must achieve the time requirement of tRPC readout in the ATLAS Muon Spectrometer Phase-I upgrade.In chapter 2,we introduce some common performance parameters which are used for time to digital converter and some typical technologies of time to digital converter,including counter method,time to amplitude conversion,analog time amplification method,crude and fine time method,time stamping time to digital converter,and so on.We also discuss the relative merits of these technologies.The time stamping time to digital converter has many advantages,such as high precise time resolution,multiple continuous measurements and short latency,et al.So this method is widely used in the high energy physics experiments.In chapter 3,we present the HPTDC ASIC chip which is designed by CERN micro-electronics group.This chip is chosen to be used in the time to digital conversion system of tRPC.We do the latency simulation of HPTDC by using its Verilog simulation code which is provided by CERN micro-electronics group.Some latency simulations are done in order to find out the reasonable parameter settings of HPTDC for getting the required time of tRPC readout,including different core clocks,different mapping of HPTDC and output of tRPC,different simultaneous hits,different measurement mode of HPTDC.From the latency simulation results,we get the reasonable parameter settings of HPTDC to make its can meet the time requirement of tRPC readout.To make sure the latency of HPTDC is in the range of 360 ns to 435 ns,the core clock of HPTDC can be set to 80 MHz,using alternating mapping and leading edge mode or pair mode.In chapter 4,we present the design of HPTDC and GOL test board.The latency of HPTDC is studied based on this test board.Firstly,we describe the detail design and function of this board.Then,we build a testing platform by using Xilinx KC705 FPGA evaluation board.Based on this testing platform,we finish the latency test of HPTDC,including different core clocks,different mapping,different measurement modes,et al.The hardware test results are matching with the simulation results,verifying the parameter settings of HPTDC which are come from latency simulation,are reasonable for the time requirement of tRPC readout.In chapter 5,we make a detailed introduction of the function and configuration of GOL chip.Then,we finish the function test of HPTDC and GOL chips by using the test board which is described in the above chapter.The function test includes rate capability of HPTDC,differential and integral nonlinearity,time resolution test,time offset and heat test.According to the function test results,HPTDC can meet the requirement of tRPC readout.HPTDC can also works well with GOL chip.In chapter 6,we describe the design of time to digital conversion system of tRPC readout.According to the space requirement of BIS7 and BIS8,we present a new design scheme of conversion system which includes one motherboard and six mezzanine cards for one system.In this chapter,we also make the detailed introduction of module designs which are used in the system.Based the design of system,we assemble one motherboard and one mezzanine card.Then,we build a test platform by using Xilinx KC705 and AC701 FPGA evaluation board and finish some preliminary tests,including the output voltage of FEAST chip,differential and integral nonlinearity test,time resolution test.The test results show the output voltage of FEAST can meets the voltage requirement of conversion system,the differential and integral nonlinearity are less than 1 LSB,the time resolution of HPTDC also meets tRPC detector's accuracy requirement of less than 600 ps.Finally,in chapter 7,we conclude the research work in this thesis and summarize what we have achieved,present the future plan for this research.