Research And Development Of The Front-end Readout ASICs For CMS Endcap Timing Layer

To expand the research scope of High-energy physics experiments,the European Organization for Nuclear Research(CERN)plans to start the upgrade of the Large Hadron Collider(LHC)to the High Luminosity LHC(HL-LHC)in 2025.HL-LHC will require a longer lifetime and aim to deliver protonproton collisions at 14 TeV.HL-LHC’s instantaneous luminosity is expected to be pushed to 7.5 × 1034cm-2s-1 and the integrated luminosity is expected to be boosted by a factor of 10.LHC upgrades posed significant challenges for the Compact Muon Solenoid(CMS),for example,installing a new minimum ionizing particles(MIP)Timing Detector(MTD).MTD consists of the Barrel Timing Layer(BTL)and Endcap Timing Layer(ETL),respectively located in the space between the last layer of the Outer Tracker and the beginning of the barrel electromagnetic calorimeter(ECAL)and the gap between the Tracker bulkhead and the Phase-2 high granularity endcap calorimeter(CE).MTD can be used to measure precisely the production time of minimum ionizing particles(MIP)for jets and disentangle the approximately 200 nearly-simultaneous "pileup" interactions that will occur in each bunch crossing of the LHC.CMS ETL chooses Low Gain Avalanche Diodes(LGADs)as the sensors to provide two hits per track with an excellent time resolution of 30～40 ps,and ETL should be radiation tolerant to 1.6 × 1015neq/cm2.It is a critical challenge in the CMS Phase-2 upgrade to design the associated front-end electronics with low power,high time resolution,and tolerance to low temperature and harsh radiation.The precision timing ASIC project is led by Fermi National Accelerator Laboratory(FNAL)in collaboration with several universities and institutions worldwide.This dissertation describes the ETL Readout Chip(ETROC),the first chip developed in a 65 nm CMOS process to handle a 16 × 16 pixel matrix and provide signal processing and data readout logic to match the LGAD.The power budget is 1 W per chip.We adopt the simple analog front-end circuits,the timing algorithms with sleep mode and self-calibration,and clock gating,to significantly reduce the static power.For radiation consideration,we use the enclosed-gate layout transistor(ELT)library provided by CERN.The Triple Modular Redundancy(TMR)and the auto-correction techniques are also applied in important digital circuits.The major works and innovations are as follows:1.The analog front-end circuits dedicated for the LGAD with the lowest power consumption have been implemented in a 65 nm CMOS technology.The preamplifier is a regulated cascade(RGC)TransImpedance Amplifier(TIA).The total power consumption of the single-channel analog front-end circuits is within 1.8 mW with a time resolution below 30 ps.2.An extreme low-power TDC has been designed using a single Gated Ring Oscillator(GRO)and a TDC controller with sleep mode.The TDC controller is activated by the leading edge of the hit pulse and then generates the gated signals.The dynamic power consumption of the TDC controller is 353 μW,while the static power consumption is only 54 μW.Test results indicate that the TDC block consumes only 97 μW at 1%hit occupancy.In addition,the TDC measurement time window is programmable and extended to 12.5 ns,enabling identifying and searching for long-lived particles.3.In this dissertation,we proposed an in-pixel automatic threshold calibration,which can quickly set an optimal threshold for timing measurement to mitigate the baseline dispersion due to temperature,radiation,process,etc.A complete calibration process takes about 35 ms with a 40 MHz clock.4.We adapted the Phase Locked Loop(PLL)inside the lpGBT project and designed a radiationtolerant Automatic Frequency Calibration(AFC)block to develop the low-jitter and multi-frequency clock generator for the ETROC.Lab tests indicated that ETROC PLL provides the random jitter within 2 ps(RMS),and the Time Interval Error(TIE)jitter is measured to be within 8 ps(peak-to-peak).The PLL circuit itself also performed stably during irradiation.5.We also proposed a scalable I2C-based slow control interface to ease the routing shortage due to thousands of registers and simplify the layout complexity.The performances of prototype chips named ETROC0(single-channel analog front-end),ETROC 1(4 × 4 pixel matrix),and ETROC PLL(clock generator)have been extensively evaluated in lab tests,proton beam tests,and radiation tests and fulfill the challenging requirements.A test chip named ET2_test,implementing the simplified version of the scalable I2C-based slow control interface,has been submitted and will be tested at the end of this year.The next iteration of the ETROC series,ETROC2,has a 16 × 16 pixel matrix and is being implemented and planned to be submitted in the first quarter of 2022.