Research On Low Power Analog-to-Digital Conversion Technology For Time-domain Sparse Signal

Sensors are ubiquitous in modern society.In sensor networks,the use of various sensor devices produces a large amount of data,which need to be acquired,processed,stored and communicated in an efficient way.In applications such as agricultural monitoring or smart watches,the sensor system powered by limited capacity battery or solar panel has strict constrain for power consumption.Low power consumption is the premise to ensure the equipment's endurance and effective operation.In such signal acquisition system,the signal acquisition is determined by the Nyquist Sampling principle.However,since the sensor input signal is usually sparse in time domain,the sampling rate of a Nyquist rate ADC(Analog-to-Digital Converter)is much higher than the information rate of the sensored signal.The wide bandwidth of the ADC makes the power efficiency limited.In order to meet the requirements of low power in sensor application,the low power analog-to-digital conversion technology suitable for time domain sparse signal is studied in this dissertation.Successive-Approximation-Register ADC(SAR ADC)is the core ADC architecture for the studied low power analog-to-digital conversion technology based on time domain sparse signal.The in-depth study of the key technology for low power consumption mainly includes: the correlation between the feature information of the input sparse signal and the SAR-principle related power consumption of the ADC;the mathematical power model of low power SAR ADC related to the input signal features;low power circuit design of SAR ADC core modules;compressed sensing SAR ADC architecture and theory analysis;Power Shaping successive approximation algorithm and thereby circuit design.Following are key highlights:(1)Studied in depth on the correlation between the input signal sparsity and architecture of SAR ADC which is designed for low power sensor applications,and settled up a power model of SAR ADC which takes time sparse signal as input.When the input signal is time-domain sparse with a limited bandwidth,the correlation of the signal itself makes the ADC samples also have the time domain correlation.Through the detailed analysis of the basic principle of SAR ADC and the key circuit blocks,the relationship between the power consumption of SAR ADC and the main performance of circuit modules is expounded.It further analyzes and explains that when the input signal is time domain sparse,each module of SAR ADC may adjust the operation mode according to the correlation of time domain signal to minimize the power consumption.(2)The worthy technical breakthrough is to propose a Power Shaping Successive Approximation algorithm and duplex architecture compatible with the compressed sensing sampling algorithm.The basic idea of Power Shaping is the bitcycle dynamic adjustment of the SAR ADC based on the dynamic adjustment of SAR ADC prediction window according to input signal feature and bandwidth.Because the Power Shaping SAR ADC is not only a Nyquist ADC,but also reduces the working frequency of the internal SAR algorithm,thus it realizes the distortion-free reconstructable and the full bandwidth ultra low power SAR ADC design,which highlights the simultaneous of the Nyquist bandwidth and power consumption level of compressed sensing ADC.In terms of circuit design,the input sampling network of the Power Shaping SAR ADC integrates the PRBS mixer,making it compatible with the compressed sensing sampling algorithm,which extends the ADC into biomedical application.The fabricated and tested Power Shaping SAR ADC reflects the Power Shaping curve,which verifies the power shaping SAR algorithm.(3)The design and physical verification of a low-voltage and low power 12 bit 20 kSPS Power Shaping SAR ADC prototype is completed.The SAR ADC is based on the Power Shaping SAR algorithm,which realizes the ultra low power consumption of the nW level.At the same time,in order to enable the ADC to be embedded into the compressed sensing acquisition system,the design integrated the sampling network with PRBS mixer.The ADC is designed and fabricated with 55 nm CMOS standard logic process.The test results show that the power consumption of the chip is as low as 204 nW,the effective number of bit is 10.7bit and the figure of merit on power by walden is as low as 6.18fJ/conv-step when the 0.6V power supply voltage is applied.Both the sine wave signal and the ECG signal are used to verify the Power Shaping Successive Approximation algorithm.The measurement proves circuit design of the ADC and the proposed algorithm.