Low Power Analog to Digital Conversion using Time Interleaved Passive Sigma Delta Modulators Powered by Integrated Photovoltaics

Energy harvesting sensor nodes are often volumetrically constrained (< 5 mm3) but must deliver useful power to a variety of analog and digital subsystems. Depending on the energy scavenging transducer, a sensor node complemented with an energy harvesting system can expect to generate between 10 nanowatts and 10 microwatts in small volumes. Energy harvesting through photovoltaics provides the most consistent source of power, either through indoor or outdoor lighting, for energy-constrained microsystems, and can easily output 10 microwatts of power based on the amount of light input into the system. The focus of this work is to develop low power and low-voltage (subthreshold) analog to digital converters (ADCs) that maximize the die area available for integrated photovoltaics. Tradeoffs such as increasing area for performance have been explored with the development of time-interleaved (TI) passive sigma delta modulator- based ADCs. Two time-interleaved (TI) passive sigma-delta modulator-based ADCs, a two-channel and a four-channel modulator design, have been fabricated in 180 nm CMOS and evaluated for use in an energy-constrained sensor node. The designs demonstrate an increase in signal-to-noise and distortion ratio (SNDR) compared to a previous non-interleaved design, without significantly increasing the resulting ADC power consumption. Results indicate that trading area for performance has significant benefits, with a 0.5 bit improvement in ENOB resulting for every doubling of interleaved ADC channels. Overall, the 4-channel design has the best performance in terms of the energy/conversion step figure-of-merit (FOM). With a 400mV supply voltage, an effective sampling frequency of 100 kHz (OSR=8.3), and a Nyquist bandwidth of 6 kHz, the FOM is equal to 124 fJ/Cs. For an operating mode of 700mV supply voltage, an effective sampling frequency of 1.6 MHz (OSR=133.3), and a Nyquist bandwidth of 6 kHz, the FOM is equal to 208 fJ/Cs. The design consumes 11.1 nW at 400mV and 652 nW at 700mV with the described parameters, respectively. The ENOB is calculated to be 3.9 bits at 400mV and 9.0 bits at 700 mV. The ADC can operate with input voltages that are above full-scale due to the attenuation provided by the passive low-pass filter at the center of this design. Results also demonstrate that DSP hardware that implements calibration for sample-and-hold nonlinearities, gain, timing and bandwidth mismatches for time-interleaved passive ADC channels can show significant improvement in SNDR and ENOB, and operate within power budgets supplied by photovoltaic energy harvesting. The conjugate gradient method is proposed to compensate for jitter in an optically-delivered sampling clock generated by a subthreshold optical CDR circuit. Testing of the proposed ADC system was performed using a fixed supply as well as energy harvesting photodiodes.