Research And Design Of Recurrent Neural Networks Based On Hybrid CMOS/Memristor Circuits

With the development of nanotechnology,highly-integrated neural network circuits become possible.Although CMOS technology continues to advance,there are still many unavoidable problems with CMOS-based neural networks:volatile on-chip synaptic information is stored;CMOS neural networks require additional devices for neuron accumulation operations.This makes it difficult to meet the highly-integrated requirement for CMOS-based neural networks.In order to improve hardware integration and reduce network power consumption,a memristor-based neural network is proposed.Mem-ristors have the characteristics of low power consumption,small size,integra-tion of computing and storage,and are suitable for hardware implementation of neural networks.In this thesis,memristor is used to calculate the characteristics of memory integration,and the memristor cross array structure is improved and analyzed to make it more accurate to store weights and bias values.Combined with the memristor's corresponding coding scheme,it can be realized.Product operation process.According to the improved memristor cross array structure,this paper also designs memristive CW-RNN circuit structure,which can complete the basic operation process of CW-RNN.The state values of the neurons are directly stored in analog form using the sample-and-hold circuit to avoid a single analog-to-digital conversion process.This structure design area is 81.128um2,and compared with the computing performance of a computer,this circuit structure is faster and consumes less power.Because there is error in the writing of the memristor,in order to ensure the reliability of the memristor-based CW-RNN,a control circuit of writing is designed so that the memristor write weight is more accurate and the classifi-cation accuracy is higher.According to the frequency control characteristics of CW-RNN,a frequency control circuit and a general-purpose CW-RNN circuit are designed.This general-purpose CW-RNN circuit structure can completely simulate the CW-RNN operation process.Simulation results show that the circuit structure proposed in this thesis improves the computing speed by 2 orders of magnitude without losing the classification accuracy.The neural network architecture constructed by the CMOS hybrid memristor changed the design of the separation between the traditional storage unit and the computing unit,and obtained high computational performance,which provided a certain theoretical basis for designing accelerators for other deep neural networks.