| In recent years,GPU has become a multi-threading and highly parallel platform for high performance computing,and it is widely used by applications that have parallel features.In GPU,multiple threads can run in parallel with executing the same instructions.However,for applications with irregular data structures,the behaviors among threads are not always the same.For instance,when threads access the L1 data cache,requests generated by threads need to access different cache-lines.This scenario is called memory divergence.In addition,when threads running together arrive at a branch,some threads jump to one path while the remaining threads jump to the other path.This scenario is called branch divergence.Memory divergence makes the size of requests much smaller than the cache-line size,degrading the efficiency of L1 data cache.Branch divergence makes the utilization of hardware resources of GPU low and wastes the bandwidth of the memory system.Furthermore,with the demand of higher bandwidth of the memory system in GPU,the energy consumption of the main memory is also increasing rapidly,which will be a challenge for the design of the future GPU.To improve the efficiency of L1 data cache,a novel cache architecture that support both fine-grained and coarse-grained cache-line management is proposed for L1 data cache.Fine-grained cache-line management works for applications with irregular memory access patterns,while coarse-grained cache-line management is for applications with regular memory access patterns.The tags that is used for fine-grained cache-line management are stored in the unused shared memory of GPU.This cache architecture improves the efficiency and bandwidth utilization of the memory system.Consequently,the performance of GPU is raised as well.In order to solve the problem of low hardware resources utilization induced by branch divergence,a mechanism named thread-lance shuffled compaction is proposed in this thesis.When branch divergence happens,the idle lanes of one path can be filled by threads located in any lanes,which reduces the number of idle lanes and improves the hardware resources utilization of GPU.Moreover,a scheduling policy is also proposed to alleviate the overhead of barrier synchronization resulted from compaction.To support this compaction technique and scheduling policy,the register file and the stack which is used to store the branch information are modified.To solve the challenge of GDDR5,DRAM manufactures develop a new memory technique,HBM.HBM is a 3D memory,who has higher bandwidth,lower energy consumption and larger capacity than GDDR5.Furthermore,two new features are introduced in HBM,dual-command and pseudo channel mode.However,the experiment results show that neither these two features can bring notable performance improvement.Therefore,a new approach that combines pseudo channel mode with a cache architecture that supports both fine-grained and coarse-grained cache-line management is proposed to explore the advantage of pseudo channel mode in applications with irregular memory access patterns. |
