The Research On Low Jitter PLL For High-performance CPUs

Asthetechnology processof semiconductor enters nanometerera, theprocessor per-formance has been improved dramatically by the process advance. As a result, the pro-cessor frequncy increases accordingly. Most of the leading CPUs are working at a speedof several gigahertz. Among them the IBM Power7+processor is a remarkable repre-sentative, whose highest working frequency is more than5.5GHz. The high frequencysets a very strict requirement on the stability of CPU clocking system. Even a tiny jitteron the clock might cause a disastrous concequence, which consequently leads to perfor-mancelossorevenfunctionfailure. Inmodernprocessordesigns,thePhase-Locked-Loop(PLL) plays an unsubstitutable role in almost all of the modern CPUs as the clock gener-ator and works as the source of clocking system. Distinguishing from other applications,inside a high-performance processor, the clock signal stability is affected by the execrableenvironment, such as energy-rich noises and drastic temperature changings. Both theseelements disturb the jitter performance of PLLs very much. Besides, the internal com-ponents of PLLs also impact the jitter closely. Hence, it is an essential for researchers toconsider both the’internal’ and’external’ factors which cause PLL jitters on the basis ofCPU overall performance.Basedontheattributesofhigh-performanceCPUsandtherequirementstoPLLs,thisdissertation investigates the principles of how the external elements, such as power noiseand temperature, and the internal components, such as the Voltage-Controlled-Oscillator(VCO), affects the PLL performance and increase the signal jitters. After that, this dis-sertation comes up with a series of solutions on those problems. The main contributionsof this disseration are summarized as follows:1. The PLL’s jitter performance is analyzed by standing on the viewpoint ofCPUs, and the external and internal factors of jitter generation are extracted, andthe technical solutions for low-jitter PLL design in CPU chips are proposed.Targeting on the high-frequency-low-jitter clocking system for high performanceCPUs, this dissertation investigates the PLL jitter problem on a broad view by takingboth internal and external factors which affects the clock signal stability into consider-ation. This dissertation extracts the relationships between the PLL jitter and the’exter-nal’/’internal’ elements, such as power noise, bias, temperature, VCO structure, and so on, and use those relationshps to set the optimization target for the low-jitter PLL designs.2. TooptimizetheloadofPLL,thisdissertationproposesaPLLframeworkwithan embeded Low-Dropout regulator (LDO) structure as the power supply. A fastresponse Current-Control LDO (CCL-LDO) model is then built and an octagonalmesh wide-transistor layout structure is proposed to optimize the threshold voltagedrift in the LDO physical implementation.To restrain the influence of power noise within the CPU, a PLL framework with anembeded low-dropout regulator power supply is proposed. By adopting the”where gen-erates, where uses” principle in the proposed PLL design, the possibility that an externalnoise couples into the internal PLL power supply network has been minimized. As a keycomponent, a fast response CCL-LDO is proposed as well to provide a smooth and cleanpower supply to the PLL circuit. By taking the advantage of fast response capability ofcurrent signal, the CCL-LDO can greatly increase the transient reponse speed of LDO cir-cuit and provides a stable and clean power supply voltage for oscillating loads like PLL,which reduces the jitter possiblity from the’external’causes. Experimental results thatusing CCL-LDO supplies charge-pump and VCO circuits shows that the phase noise canbe reduced about-40dB to-60dB, which means the PLL jitter is reduced dramatically.Besides the power supply structure, the wide power-transistor is one of the perfor-mancelimitingfactorinLDOaswell. Anoctagonalmeshwide-transistorlayoutstructureis proposed in this dissertation, which can reduce the threshold voltage drift in the sub-strate and assure the threshold voltage stability of wide power transistor.3. To increase the temperature stability of PLL circuit, two bandgap referencestructures optimized for the harsh environment in CPU chips are proposed in thisdissertation.Itiswellknowthatthebiasvoltage/currentsignalissensitivetotemperaturechanges.In order to increase the temperature stability, the bandgap reference is utilized as the biasgenerator in PLLs. The bandgap reference biasing techniques are studied in detail inthis dissertation: First, the’base-emitter’ branching effect in the core circuit is discov-ered and analyzed, and a’base-emitter’ current compensation scheme is proposed; Then,a temperature-drift compensating scheme is proposed by utilizing temperature-resistoreffect of difference materials; And finally, a configurable bandgap reference circuit isproposed. Based on that, two bandgap reference voltage/current source circuits are im- plemented with high temperature stability. Theory analysis indicates that the proposedbandgap reference biasing circuit can stabilize the DC working conditions (e.g., powersupply voltage, current, etc.) of PLL in large temperature fluctuations and the tempera-ture stability can achieve1ppm C level.4. The factors that affect the balanced working condition of VCOs is analyzedand the’Native Jitter’ phenomenon of VCOs is discovered. To eliminate the nativejitter, an inter-locked dual-loop and feed-forward self-cross multi-loop structures ofVCOs is proposed.This dissertation explores the causes of’Native Jitter’ of VCOs, analyzes the princi-ples of the generating of native jitter. To eliminate the native jitter, an inter-lock dual-loopstructure is proposed to balance VCO’s average Isscurrent. In addition, a feed-forwardself-cross mulit-loop VCO is proposed base on the former structure for further optimiza-tion. The feed-forward self-cross multi-loop VCO is a fully symmestric single-end VCOwith even stages delay cell, and its current is well balanced and has no oscillation. Thusthe native jitter is immuned. Experimental results indicate that the proposed structure cansuppress more than80%”native jitter” and has a great linearity.5. To eliminate the impact of supply voltage noise and control voltage noise, aVCO with embeded low-pass LC filter is proposed.There always has noises on the power supply and control signals of VCOs. Thisdissertation analyzes the propogating pathes within VCOs, and finds a communal nodeof the two pathes. To eliminate the noise, a VCO with embeded low-pass LC filter isproposed. To stimulate the process time and reduce the manufactering cost, the activeinductor is adopted. With this low-pass LC filter, the phase noise of VCOs is reducedabout30%. As a result, the jitter of PLL is reduced correspondingly.To be a summary, a PLL in40nm technology process is designed in this dissertationto demonstrate the above technical optimizations. The result shows that the jitter(RMS)is significant reduced: for the electrical-element induced jitter, the anverage squre root isdecreased about66%; for the thermal-element induced jitter, the anverage squre root isdecreased about58%.