| Semiconducting memory and logic devices are playing a more and more important role in today’s information technology such as computing, communicating, displaying and so on. And the semiconducting memory devices have been developed rapidly in the past few years. In this manuscript, we focus on the physical mechanism and device characteristics of the new generation non-volatile memories, and the main content is listed as below:1. With the increasing integration of flash memory chip, the feature size of the cell decreases at the same time and lies below20nm by the end of2013. To guarantee the data reliability, traditional flash memory which employs polysilicon as its floating gate still possesses a tunneling oxide layer with7nm in thickness to eliminate charge leakage. As a result, it becomes a bottleneck and brings about many performance degradations such as the low speed (ms), high operating voltage (>15V), poor endurance (104) and so on. However, the discrete charge storage memory, using laterally isolated quantum dots instead of continuous polysilicon as the floating gate, will solve these problems effectively. The charges stored within the quantum dots can’t transfer between each other and will never leak out completely through one sneakpath generated in the tunneling oxide layer. As a result, ultra thin tunneling oxide can be used to remarkably decrease the operating voltage and raise up the speed, meanwhile with no reliability degradation occurred. We have successfully fabricated the silicon nanocrystals (nc-Si) floating gate flash memory cell on the0.13μm standard CMOS process line in SMIC. The cell length and width are0.176μm and0.16μm, respectively. The thickness of tunneling oxide is about3.5nm. The average size of nc-Si is about12nm with the density of2×1011cm-2. The cell gets an "OFF" current as low as200fA and the subthreshold swing is about0.14V/decade. After programmed and erased by±7V/10μs pulse, respectively, the cell can get a memory window of about1V, which is large enough for a typical sense amplifier to detect. And the window will be more than1.3V if operated by±7V/lms pulse. Besides, the cell shows a very good immunity to the disturbance of low bias and good data retention characteristics. More importantly, the pulsed endurance testing demonstrates performance up to107P/E cycles, which is much higher than the traditional flash memory cell (104). Generally, our nc-Si floating gate memory exhibits very wonderful characteristics such as low operating voltage, low power consuming, high speed, long endurance and so on, which has already been used in our upcoming8k bits nc-Si flash memory chip with NOR structure.2. With the cell size decreasing below16nm, the state-of-art charge-based flash memory will face its scaling limit. And if taking the discrete charge storage as the evolution of traditional flash memory cells, the next generation universal memory which is based on the physical state switching should be considered as a revolution of them. Among many uprising universal memories, the resistance switching random access memory (RRAM) is a very hopeful candidate. It gets so many advantages comparing with conventional charge-storage memory, such as simple M/I/M structure, high density integration (1nm cell size with crossbar structure), super high speed (ns), much lower operating voltage (-1V), much longer endurance (1012) and so on.We choose SiOx as the insulating layer, because it shows a high compatibility with current CMOS process and is richly endowed with the nature of low costing. Through I-V measuring, the Pt/SiO0.73/Pt structure shows a very good resistive switching characteristic. The reset and set voltage locate around0.7V and1.7V, respectively, which are all very low and also very uniform. The memory window (current ratio read at200mV) is stable and as high as104. The device can be operated by more than100cycles, showing a good endurance characteristic. And the memory window shows no obvious degradation after12hours at80℃. Besides, we also found the x dependent two kinds of different resistive switching behaviors in SiOx films with different x component. When x<0.80, the forming/set operations need a current compliance and the reset voltage Vreset is lower than set voltage Vset-We call it as "normal unipolar region". However, when x>0.95, the operations don’t need a current compliance and Vreset is higher than Vset, with the current level in both of HRS and LRS much lower than that in the "normal unipolar region". We usually call it as "abnormal unipolar region"3. So far, there are still many arguments about the resistive switching mechanism of SiOx films. Here, we propose the silicon dangling bonds (Si-DBs) percolation model to explain the observed switching behaviors. It is based on that the as-deposited SiOx films contain a large number of pre-existed Si-DBs and the Si-O bonds in SiOx films are polar and covalent. As a result, during the forming or set processes, the biasing electric field will break the Si-O bonds configurations in SiOx films to form new Si-DBs. When the total Si-DBs reach the threshold value, the Si-DBs percolation path will be formed which can be considered as a mini-band formed near the middle of SiOx band-gap. The electrons can be transported through the mini-band by hopping process, and the device is switched into low resistance state (LRS). During the reset process, much higher current will flow through the percolation path because of the low resistance, generating sufficient thermal energy and leading to the thermal re-oxidation of percolation path, and the device is switched back to high resistance state (HRS). During the subsequent set process, because of the partially re-oxidation of Si-DBs in percolation path, the set voltage is usually much lower than the forming voltage.Based on the microstructure analysis such as X-ray photoelectron spectroscopy (XPS) and electron spin resonance (ESR), and taking into account of the Anderson localized states conductivity theory, we consider that the transition phenomenon of switching behaviors in SiOx films is originated from the microstructural changes in the Si-DBs percolation path with different x component. Because of the dominated ·Si=Si3DBs in percolation path, the mini-band is relatively narrow and the density of states is relatively high, resulting in a sufficiently high conductivity in LRS. However, for the "abnormal unipolar region", the·Si=Si2O,·Si=SiO2,·Si=O3DBs dominantly contribute to the mini-band, resulting in the increase of the width of the mini-band. Besides, the density of states in mini-band will decrease because of the mini-band widening effect, these will lead to a remarkable decrease of conductivity in LRS and as a result, the current level in LRS will decrease. Moreover, based on the Si-DBs percolation path model, the mechanism for reset processes is the thermally re-oxidation of a few parts of the Si-DBs by the joule energy generated by reset current. As mentioned above, in the "abnormal unipolar region", the conductance in LRS is pretty low and no current compliance is needed in the forming/set processes. Therefore, a higher reset voltage must be applied to generate sufficient thermal energy for thermal re-oxidation. Consequently, in the "abnormal unipolar region", the Vreset must be higher than the Vset. |
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