The Design Of Sigma-Delta ADC In Audio Codec Device

The Sigma-Delta A/D converter,which is based on oversampling,noise-shaping and digital down-sampling technology,is a critical component of high-resolution integrated circuit device.Because of its insensitive to the non-ideal factors in circuits and its compatibility with VLSI technology,high precision,flexible and other advantage,it has become the mainstream of design technology on high-resolution ADC and has been widely used in audio,measurement,wireless communication and other fields.This paper is focused on the design of 18-bit Sigma-Delta A/D converter in audio application field with switched-capacitor technology.Base on in-depth understanding the basic principle of the Sigma-Delta A/D converters,the single-loop / high-order structure is studied in this paper and an 18-bit fourth-order feed forward Sigma-Delta A/D converter is presented.The main contributions of this paper are as following:(1)A single-loop fourth-order feed-forward Sigma-Delta modulator system structure is designed after analyzing its basic principle.After discussing the influence with variety non-ideal factors on system performance,the Sigma-Delta modulator module is designed and verified based on Maltab/Simulink.The results shown that the modulator get-120.5d B in signal-noise-rate(SNR),which is satisfied the requirement of 18-bit high resolution in ADC.(2)Each modules of the whole modulator are designed basing on switched-capacitor technology,including the low power class AB OTA,the high speed voltage comparator,non-overlapping clock generator and the feedback DAC,etc.Each module is given the design process and design result,then finished circuits design of the modulator finaly.(3)The digital decimation low pass filter which is consists by Cascade Integrator Combfilter and half-band filters are designed.The amplitude-frequency characteristics of each filter are given and the whole filters are presented in Maltab/Simulink environment,in addition,the half-band filter's coefficients are represented in CSD.The Sigma-Delta modulator in this paper are designed and realized based on 0.18-?m 1P6 M N-well P substrate CMOS process and its power supply voltage is 1.8V.over sampling rate is 128,the sampling frequency is 6.144 MHz,the signal bandwidth is 20~20KHz.Under the condition of the effective signal bandwidth,the output signal-noise-ratio(SNR)in circuits level can achieve-112.5d B,match the requirement of the accuracy,the layout area of this Sigma-Delta modulator is 560?m×260?m.The input sampling frequency of the digital decimator low pass filter is 6.144 MHz and the output sampling frequency is 48 KHz.The passband cutoff frequency of the filter is 20 KHz,and the maximum passband ripple is 0.00003 d B.This design was fab-out from SMIC 0.18 um CMOS technology and was assembly also by SMIC.After final test,we get the test result as the THD+N(total harmonic distortion + noise)are better than-90 d B in 20 KHz passband,the dynamic range is better than-100 d B and the ENOB is 18 bit.The test result is matching the expected value of design.