The Models And New Structures Of Charge-Mode High Voltage SOI Device

SOI HVIC (High Voltage Integrated Circuit) is widely applied to power ICs owingto its high speed, high integration level, high reliability, perfect irradiation hardness andeffective isolation. The low vertical breakdown voltage (BV) of SOI lateral high voltagedevices limits its application in high voltage power integrated circuit. The breakdowncharacteristics of SOI high voltage devices have been studied by device workers.Enhancing the electric field of dielectric buried layer (EI) is an effective way to increasethe vertical BV. ENDIF(Enhanced Dielectric layer Field) principle was presented by theauthor's research group, of which introducing interface charges is attractive.In this thesis, based on the continuity of electric displacement with interfacecharges, the electric fields and potentials of charge-mode SOI ENDIF devices areresearched. The mechanism of charge-mode SOI LDMOS ENDIF principle is analyzed.One analytical model of the electric field distribution for SOI devices with interfacecharges is presented; and the other analytical model of the breakdown voltage for SOIdevice with a thin top silicon layer is proposed. Based on the above two models, thenovel high voltage charge-mode device structures of SOI nLDMOS,SOI SJ LDMOSand in particular SOI pLDMOS have been proposed, and the related experiments aremade. The main innovative work is as following:Firstly, the electric field with interface charge model is proposed. The verticalpotential in drift region is a parabola approximation. The second boundary condition ofelectric displacement continuity with interface charges is applied on the buried layerinterface. The analytic expression of the electric field and potential in drift region areobtained. The analytical model of dielectric layer electric field in drain region is denoted.Theoretically, using the above model, LVD N~+I (Linear Variable Distance N~+ChargeIslands) SOI nLDMOS and N~+I SOI pLDMOS are presented. The influences of deviceparameters on the electric field, potential, specific on-resistance Ron,spand BV arediscussed in the above model. EIand BV are600V/μm and612V of LVD N~+I SOI,respectively. EI=502.3V/μm of N~+I SOI pLDMOS is obtained on a2-μm-thick silicon layer over a0.375-μm-thick buried layer. The N~+I device has the BV twice as high as ofthe conventional SOI LDMOS, maintaining the low Ron,sp.Secondly, the voltage of thin silicon layer model is presented. Based ontwo-dimensional Poisson equation of the conventional SOI device, the drift regionlateral electric field in the thin silicon layer is assumed to be a constant. For the SOIdevice with a linear variation of doping in the thin Si layer, the dependence of the BVon the impurity concentration under the drain is investigated by using idealcharge-mode ENDIF, from which the RESURF condition is deduced. The optimizedmethod of drift region electric field is obtained. Based on this model, the linear shallowjunction TSL (Thin Silicon Layer) SOI SJ (Super Junction) nLDMOS is reported. TheEIand the BV of TSL SOI are530V/μm and552V in30μm length drift region and1μmthick dielectric layer. The low Ron,spand the BV of690V are obtained by experiment.Finally, inversion/accumulation carriers charge-mode, ionized charge-mode,hybrid charge-mode of nLDMOS, pLDMOS and SJ based on above model are reported.(1) Charge-mode high voltage SOI nLDMOS. Interface dynamicinversion/accumulation charges with high concentration enhance effectively the electricfield strength in dielectric buried layer and increase BV. Four new device structures arepresented, such as SBO PSOI (Step Buried Oxide Partial Silicon-on-insulator SOI)nLDMOS and PBN~+SOI (Partial Buried N~+-layer SOI) nLDMOS. For SBO PSOI, theBV of244V and EIof114V/μm are reached, and the surface maximal temperaturereduces by34.76K in comparison with conventional SOI. The EIand BV of PBN~+SOIare improved by186.5%and45.4%compared with those of the conventional SOI,respectively.(2) Charge-mode high voltage SOI pLDMOS. The low substrate potential ofconventional pLDMOS can't deplete assistantly the drift region, resulting in the low BV.Charge-mode SOI pLDMOS can solve the issue of the low BV and high Ron,spbyintroducing interface charges. Three novel device structures of ABE SOI and FBL SOIare presented. For ABE SOI (Adaptive buried electrode SOI), the EIand the BV are545V/μm and-587V, respectively, and Ron,spis reduced by79.5%compared with that ofthe conventional SOI LDMOS, with a low self-heating effect.(3) Charge-mode high voltage SJ SOI LDMOS. For SOI SJ LDMOS, the tradeoffof BV and Ron,spis improved, which breaks the "Silicon Limit" in conventional SOI SJ LDMOS. However, when SJ technology is applied in lateral power devices, SAD(substrate-assisted depletion effect) destroys the charge balance of P-and N-pillar,resulting in a low BV. Charge-mode high voltage SJ structures can eliminate the SADand enhance the BV. Four kinds of new structures are proposed, such as:DT(DielectricTrench SOI), EI=600V/μm and BV=-237V are obtained on2.5-μm-thick topsilicon layer and T-DBL (T-Dual Dielectric Buried Layer SOI), EI2=515V/μm isobtained on15μm drift region and BV is increased to302V.