New Structure And Model Of High Voltage MOS-gated Power Devices With Low Power Loss

As a full-controlled power device, the MOS gate-controlled power device is desirable for the merits of high input impedance and its easiness to drive. Hence, the MOS gate-controlled power devices account for the largest share of the discrete power device market and are also the key component of power intergrated circuit (PIC),serving as the major power unit for AD-DC, DC-DC conversion and power driving system. It is essential for power devices to achieve both high breakdown voltage (BV),low power loss, as well as high power density. As main force of power devices, the power MOSFETs encounter the issue of the tradeoff between BV and the specific on-resistance (Ron,sp), that is, Ron,sp?BV2.5. Particularlly,this tradeoff is more severe for the P-channel MOSFET due to the lower mobility of holes than that of electrons. The reduced surface field (RESURF) technology and the superjunction (SJ) technology can effectively reduce the Ron,sp of power MOSFETs without compromising the BV. The trench technology can further reduce the required area of power devices and is thus beneficial for minimizing the chip size and increasing the packaging density. However,the existing RESURF principle cannot be directly applied to the design of silicon-on-insulator (SOI) p-Channel LDMOS (pLDMOS), due to its different electrode connection compared to that of nLDMOS in practical application. The RESURF and SJ technologies offer very limited effect in decreasing the lateral cell pitch of the device.There is still lack of accurate analytical model as theoretical guidance for the design of high voltage trench LDMOS, to our best knowledge. Owing to conductivity modulation effect, the insulated-gate-bipolar-transistor (IGBT) are superior in applications requiring high voltage and large current. Particularly, the reverse-blocking (RB) IGBT can offer both forward blocking and reverse blocking capabilities, and is desiable for the matrix converter since the series diode can be omitted, yielding the reduced conduction loss,improved efficiency, and decreased volume and cost of the matrix converter for direct AC-AC conversion applications. However, the present RB-IGBTs are mainly based on the non-punch-through (NPT) structure that suffers from both high on-state voltage (Von)and large switch energy loss.In this thesis, aiming to address the above foundamental issues for MOS-gated power devices, the high voltage LDMOS and RB-IGBTs are researched from the aspects of theorectical model and device structure, with breakthoughs by approaches of new mechanism, new material, and new structure. The innovation of this thesis is that an analytical BV model is developed and three new device structures are proposed based on this model.1. Universal Analytical BV Model for Trench LDMOSTsFor both high BV and low Ron,sp of the trench LDMOS, we develop an universal analytical model that can be applied for both variable-k dielectric trench LDMOS and uniform dielectric trench LDMOS. We present a novel decoupling method with the concept of virtual equipotential field plate for the complex electric field of the trench LDMOS. By solving the 2-D Poisson equation, we derive the analytical expression of electric field along the critical path in the bulk of the trench LDMOS. The analytical BV model is developed and the optimal RESURF conditions are obtained. The anatytical results from the model agree well with simulation results. Based on the analytical model,the internal relations between key parameters and BV are theorectially revealed. The design and optimization rules for high voltage trench LDMOS are obtained. (The study is published in IEEE Transactions on Electron Devices (T-ED), 2015, 62(10):3334-3340)2. Ultralow Specific On-Resistance Variable-k Trench nLDMOSBased on the analytical model, we propose a novel variable-k trench LDMOS with the concept of combination of heterogeneous materials. The new structure features a variable-k trench introduced in the drift region. According to continunity of the electric displacement, the abrupt change of the k value inevitablely lead to abrupt change of electric field and thus induces new electric field peak at the interface between different dielectrics, yielding the optimal electric field distribution in the bulk. Traditional approach for reducing Ron,sp is mainly by increasing the drift region doping. Differently,the vertical design concept for lateral power device is utilized here for VK-P LDMOS.The lateral high voltage is fully supported by the bulk silicon region around the trench.Therefore, the required lateral device dimension is effectively reduced. As a result, the Ron,sp is significantly reduced, breaking through the 2.5th silicon limit. At the high voltage range of 600V?900V, the proposed structure delivers an utralow Ron,sp of 15.8?37.7m?·cm2, with the figure of merit (FOM=BV2/Ron,sp) reaching 21.8MW/cm2,superior to existing trench LDMOS devices. (The study is published in IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), Hawaii,2014, 189-192 and IEEE T-ED, 2015, 62(10): 3334-3340)3. Conduction-enhanced high voltage SOI pLDMOS mechanism and new structureTo address the issure of suppressed RESURF effect of SOI pLDMOS due to its special electrode connection, we propose the RESURF-enhanced trench (ERT) SOI pLDMOS. The new structure employs the U-shaped P-drift region around the oxide trench in N-type SOI layer. In the off-state, both the N-SOI layer and the vertical extended gate in the oxide trench multidimensionally assist in depleting the P-drift region, effectively enhancing the RESURF effect. By analytical calculation, the conductivity enhancing factor is derived as ?Q=1.4×1012cm-2?3.4×1012cm-2. By contrast, the P-drift region dose of conventional SOI pLDMOS is only at the magnitude of 1011cm-2. The ERT SOI pLDMOS achieves a low Ron,sp of 17.5mQ·cm2 at the BV of 329V, exhibiting 79% reduction in the Ron,sp compared with that of the planar P-top structure at the same BV level. Furthermore, the new structure realizes the shielding effect of back gate biasing effect. For 300V rated device, the characteristics in the active region of ERT SOI pLDMOS can be immune to the variation of the back-gate voltage in a large range of -150V?150V. (The study is published in IEEE T-ED, 2014, 61(7):2466-2472)4. Utralow loss SJ RB-IGBTFor the issue of high power loss due to the NPT-based structure of conventional RB-IGBT, we propose, for the first time, the supeijunction (SJ) RB-IGBT. The new structure offers both high-voltage bidirectional blocking capability and the low conduction and switch loss. The device ultilizes SJ structure in the drift region and induces a shorted-collector trench (SCT). Owing to the assisted-depletion of the SCT to the N1 field-stop (FS) layer as well as the FS layer N2 at the top of N-pillar, the SJ RB-IGBT realizes the symmetric bidirectional blocking capability that is absent in FS IGBT and conventional SJ IGBT. By investigation of the current conduction behavior,we reveal the on-state characteristic distinct from that of conventional SJ IGBT. At the on-state in linear region, the SJ RB-IGBT maintains bipolar conduction mode even at high pillar doping, enhancing conductivity modulation effect and thus reducing the Von.During turn-off transient, the SJ RB-IGBT exhibits unipolar conduction mode due to the lateral built-in electric field, enabling a fast turn-off speed comparable to that of MOSFETs and thus non-tail current as well as low turn-off energy loss (Eoff). Therefore,the SJ RB-IGBT offers both merits of the large current capability of bipolar devices and the fast turn-off speed of unipolar devices. (The study is published in IEEE Electron Device Letters (EDL), 2016, 37(11): 1462-1465)It is noteworthy that we further investgate the application level characteristics of the SJ RB-IGBT for AC-AC applications based on matrix converter (MC). The dynamic behavior of the current commutation and the loss distribution of the MC using SJ RB-IGBT are investigated. Furthermore, the total power loss of the MC using SJ RB-IGBT is obtained and compared with MCs ultilizing other RB-IGBT devices. The performance superiority of the SJ RB-IGBT in AC-AC applications are evaluated. (The study has been accepted for publication in IEEE Transactions on Power Electronics.)...