Research On Key Problems Of Resilient Packet Ring And Its MAC Application Specific Integrated Circuit Design

Resilient Packet Ring (RPR) is a new Metropolitan Area Networks (MAN) technology which integrated the high QoS guarantee of SONET/SDH and the economy of the Ethernet. It can support real-time traffic as well as data traffic on optical ring networks. The main contents of the dissertation include analyze and improvement of bandwidth allocation, fairness algorithm and intelligent protection switching for RPR which are all RPR key technologies; also design and implement RPR MAC Applicated Specific Integrated Circuit (ASIC) MXRPR01-7. The main contributions of the dissertation are as follows:1. Fairness algorithm for RPR described in IEEE 802.17 standards is analyzed. The fairness algorithm defined in RPR standards has defect in bandwidth allocation and bad performance under conditions of unbalanced traffic or wrapping protection switching. In order to overcome these defects, an improvement of the fairness algorithm which is easier to implement in hardware is produced to achieve better performance. The analysis and simulation results show that the novel algorithm could overcome the former defects and get stable performance, which is also easier to implement in hardware and apply to high-speed RPR facilities.2. According to IEEE 802.17, Steering protection switching have defects of low switching speed and more packet loss; wrapping protection switching have defects of low bandwidth utilization; in addition, RPR treats all link failures as bidirectional which deteriorates the performance of steering protection switching in case of unidirectional link failure. In order to overcome these shortcomings, an integrated intelligent protection switching scheme is proposed based upon the deep analyze of the two protection switching algorithm described in RPR standards. The analysis and simulation results show that the integrated protection switching scheme can achieve better performance with higher switching speed, less packet loss, higher bandwidth utilization.3. The ASIC design of RPR MAC is studied based upon the research on RPR MAC standards. The final overall circuit design schemes are proposed and implemented. The design of the key modules and the main parameters are analyzed and completed. The software verification system is designed and implemented. It uses multi-machine communication technology to solve the problems during the process of the verification. The sample test scheme is also proposed in the thesis. The RPR MAC ASIC MXRPR01-7 has been typed out successfully.