Research On The Caching Mechanism As Part Of Memory Subsystem For Network Processors

Network processor is designed to meet the simultaneous demands of high speed packet forwarding and high program flexibility. Due to the common belief of the lack of sufficient locality in network applications and the uncertainty of its performance, caching mechanism is replaced by exposed memory hierarchy and multithreading in most of today's network processors to overcome the memory bottleneck. However, efficient utilization of these new mechanisms complicates programming and wastes system resources, which finally prevents network processors from being widely used.In this thesis, several fundamental questions are asked: (1) how does caching mechanism behave in the environment of network processor, can it bring any benefit in terms of increasing the packet throughput and reducing packet loss at relatively low cost? (2) If caching mechanism is beneficial, how can it be applied in commercial network processor products and how should caching mechanism be designed to improve its performance? This thesis makes four major contributions.(1) An experimental environment that can be used to evaluate the effectiveness of caching mechanism in network processors is set up. Simulation results show that packet processing exhibits considerable data locality. A sufficiently large cache tends to reduce the number of memory requests and thus improve the utilization of computation power of network processors.(2) A model that can be used evaluate the impact of packet arrival process on the performance of network processor is suggested. Detailed analysis shows that high level of bursty arrival is very common among packets of the same flow. Under the arrival pattern of real-life traces, both caching and multithreading mechanism can greatly improve the throughput and reduce packet loss rate. But the effectiveness of the two mechanisms is greatly affected by thread allocation policy.(3) A software-based route cache algorithm is developed for network processors with no specific optimization for route lookup. The algorithm makes use of the exposed memory hierarchy of today's network processor. Part of the on-chip high speed memory space is programmed into a caching table for temporal storage of route lookup results. Experiments show that the lookup capability of network processor can be effectively improved with only a small number of cache entries per processing element.(4) A register file and a novel memory hierarchy component, called Split Control Cache, are proposed for network processors. The register file is designed to eliminate the bottleneck in I/O system. Split Control Cache employs two independent subcaches for flow-based and application-relevant information, exploiting the different locality behaviors exhibited by the two types of control data. Software simulation shows that compared with conventional cache, Split Control Cache can not only improve the packet throughput of network processor, but also provide enough programming flexibility.