A Design Of Defragmentation Mechanism Applied In Network Protocl Processor

With the proposal of next generation 40G/100G Ethernet standard, the rapid deployment of high-speed backbone networkt, demand for high speed network is becoming stronger and stronger. In the premise of high speed and safety, it is a longterm and imperative task to seek out a suitable solution. After investigation, network security processor is considered as an effective way to solve this problem. However, the status quo is that the performace of network security processor is far behind the requirements of network security. Consequently, the research of high speed network security chip is very important.In the network security processor architecture, data access is usually through two ways. The first one is indirection operation based on descriptior and the other one is through the real data. In the descriptior application scene, descriptors are offen stored in high-speed access memory in that descriptors are frequently accessed and processed. However, the address space of high-speed access memory is limited and it is necessary to monitor and control descriptors. This paper presents a descriptor-oriented defragmentation mechanism based on a project in JiangNan computational technology institute. Based on statistical principle, the defragmentation process can adjust the distribution of descriptors stored in high-speed access memory space and avoid the processing performance decline due to the short length network packet under the bad network environment. The mechanism proposed in this paper makes the address space use of high speed access memory more reasonable. The design scheme used SRAM as high-speed access memory where control information and descriptors are stored.. The whole design scheme is carried out using Verilog hardware description language. The next steps are an analysis of function point and simulation results through UVM (Universal Verification Methodology) platform after the design specification. Logic synthesis is completed using DC (Design Compiler) synthesis tool. Then, FPGA (Field Programmable Gate Array) protype platform is built to test the whole system. Finally, the UVM platform is used to evaluate the performace of defragmentation efficiency. Experimental results showed that, in the regular network scene, the storage space can save 5% at least and in the bad network scene, the space save 66%.In this design, a hardware method of defragmentation mechanism was proposed. The usage of high-speed access memory's address space will be improved. The paper can provide technical reference for the network security protocol processor function and performance requirements.