New Study Methodology Of Finite-Difference Time-Domain And Performance Optimization For Interconnects In High Speed Integrated Circuits

With the rapid development of high-frequency high-speed very large simulated integration (VLSI) circuits, the electromagnetic effects in VLSI circuits are more and more obvious. To resolve accurately the signal integration problems of high-frequency circuit systems under the impacts of electromagnetic effects, the analysis and design for electromagnetic characteristics of interconnect and package structures in circuits are necessary. Moreover, the appearances of new structures of three-dimension integrate circuits and microwave MCM make electromagnetics problems in these structures not be neglected, which also casues the new requirements for electromagnetic simulation software being proposed. The problems rising in the real engineering offer great power to the development of computational electromagnetics (CEM). As one of the most important methods in CEM, the finite-difference time-domain (FDTD) method has been applied to every aspect in electromagnetic fields since it can implement time-domain computation directly, and it can be applied in very broad areas with relatively simple realized techniques, and one single run of simulation can provide information over a large bandwidth. The advantages of the traditional FDTD method (Yee's method) are apparent, however, the efficiency of the FDTD method is limited by the Courant-Friedrich-Levy (CFL) stability condition and numerical dispersion.To reduce the high dispersion error of the FDTD method,this dissertation proposes a high-order symplectic finite-difference time-domain (SFDTD) method. This method is a simple explicit integration time method which was originally developed to solve numerical systems derived from a Hamiltonian formulation and can preserve the symplectic structure of the systems constant. Maxwell equations can be treated as a Hamiltonian system, therefore, the SFDTD method based on symplectic integration technique is high accurate and nondissipative. The analysis of stability and dispersion of SFDTD method is roundly given. The resules show that the Yee's method is equivalent to the low order SFDTD schemes, and hence the high order schemes have lower dispersion and smaller phase error compared to Yee's method. The final numerical examples show that the high order SFDTD method can save greatly memory thanks to low dispersion.To remove the CFL stability condition of the FDTD method, this dissertation introduces a three-dimension finite-difference time-domain algorithm based on precise integration technique (PITD), too. Among all of the methods which have been proposed in the past to overcome the stability condition of traditional FDTD method, the ADI-FDTD method is the most improtant. It can eliminate the CFL limit successfully. However, in this method, the use of a large time step also increases greatly the dispersion errors. While in this dissertation, through discussing in detail the stability condition and numerical dispersion of PITD method, we discover that a larger time step than the maximum CFL limit of Yee's scheme can be adopted and the better accuracy than ADI-FDTD method can be obtained by the PITD method. The dispersion error of PITD can be made nearly independent of the time step increment. However, this method involves the computation for large matrix equations and hence requires a number of memory spaces. This dissertation also subjusts to apply the compact two-dimension technique to the PITD method to develop a new compact 2-D PITD method, which can lighten a certain extent the requirement for memory of 3-D method and avoid the computation of invertible matrix for guided wave problems.Besides the study for the new approaches in CEM, this dissertation put efforts on global interconnect design and optimization with circuit analysis method. This is because that with technology scaling, global interconnects have started to limit the overall performance of a system-on-a-chip. The transistor-centric design has been turn to the interconnect-centric design in a VLSI circuit. In this dissertation, our goal is to attain the optimization of comprehensive performances of global interconnect system by means of the best tradeoff in all performances. We firstly consider distributed RC global interconnects with repeater insertion. After analyzing deeply the impacts of the line width and spacing on interconnect RC delay, power dissipation, bandwidth and total repeater area, a user-specified figure of merit which is a delay-power-reciprocal bandwidth tradeoff formulation is proposed to calculate the optimum width and spacing of global interconnects for various ITRS techniques nodes. This methodology is also used to quantify the effect of such optimization on every performance for various technology nodes.Next this dissertation considers the double-sided shielded global interconnect structure with repeater insertion using distributed RLC models. Assuming the same size and material are adopted in the signal line and shielded line, the effects of signal line width and spacing between the signal and shielded lines on the interconnect RLC delay, power dissipation, and bandwidth et al are analyzed all the round. A user-specified figure of merit which is a bandwidth-reciprocal delay tradeoff formulation is then proposed to calculate the optimum width and spacing of double-sided shielded interconnects for various ITRS technique nodes, and the effect of such optimization on every performance is also quantified.This dissertation finally introduces the analysis and optimization problem of thermal-driven global interconnects. After the thermal models and temperature-dependent interconnect and device models are present respectively, we compute the temperature as the function of topmost global interconnect width and spacing and analyze the impacts of interconnect size on global interconnect temperature and substrate temperature, and the size as well as temperature on interconnect performances. The same figure of merit that a delay-power-reciprocal bandwidth product is defined to optimize interconnect width and spacing and quantify the effect of such optimization on interconnect performances and topmost interconnect and substrate temperature for various ITRS technique nodes.