Research On Simultaneous Multithreaded Processor Front-end

Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle. In SMT processors, functional units that would be idle due to instruction level parallelism (ILP) limitations of a single thread are dynamically filled with useful instructions from other running threads. By allowing fetching instructions from other threads, an SMT processor can hide both long latency operations and data dependencies in a thread. These advantages increase both processor utilization and instructions throughput.In SMT processors, the front-end is a critical part that includes the fetch controller, branch predictor, and level 1 cache. The performance of an SMT processor is largely depended on the design and implementation of the front-end. In this thesis, some important issues around the front-end are investigated, and the results are listed as follows.Instruction fetch policy: A new instruction fetch policy, IPCBFP, is proposed to ultilize the fetch bandwidth more efficiently. Comparing with the existed ICOUNT policy that maybe fetch too much instructions for the first selected thread whereas too less for the second, IPCBFP policy computes the number of needed instructions of the threads and fetchs them according to the computing results. With IPCBFP policy, a significant improvement of performance is obtained. Execution-driven simulation results show that the average speedup is up to 28% for the two and four threads workloads.Fetch policy with QoS: The requirements of a demanded quality of service are always claimed by the multi-media applications and some time critical programs. Till now, only several researches have addressed this issue in SMT processors, and have proposed some solutions that are all too complex to be implemented. A new solution to this issue, a QoS capable fetch policy, is proposed in this thesis. The policy uses a thread priority and a flow speed to control the number of instructions being fetched for a thread. Using this mechanism, the QoS requiring threads can fulfill their desired services, while the other threads can also obtain a try-my-best service from the processor. Simulation results show that this policy is an effective QoS capable fetch policy for SMT processors.Cache compression: In SMT processors, with the number of running threads increasing, the usable cache of a single thread decreases continually, and the number of cache misses increases, thus degrading the performance of the thread. A simple cache compression...