Research And Manufacture Of Static Induction Devices

Static Induction Devices (SIDs) mainly include Bipolar-Mode Static Induction Transistor (BSIT), Static Induction Transistor (SIT) and Static Induction Thyristor (SITH). Being one kind of novel power devices, SIDs for high operating frequency and high power application has attracted many scientists' great attention and has gained significant developments, since SIDs have many excellent electrical performance: such as low distortion, low noise, good linearity, no second breakdown, negative temperature coefficient, high output power and so on. The work in the present thesis has been carried out combining a scientific research item titled "The research and manufacture of Static Induction Device", which is sponsored by Lanzhou Science and Technology Committee. The key points in the present thesis are listed below:The disadvantages of former layouts have been analyzed and the new layouts have been designed. The new layout of LD-SIT-0603 has proposed technologic design which is quite distinct from the past. The smart design of three trenches completely solved the key problem of the trenches and mesa etching. The other new layout of LD-SIT-0703 is designed for the SITH of buried-gate with diffused source region which applied the field-limiting rings and channel stopper as the terminal shape.The BSIT with excellent I—V characteristics has been fabricated successfully. The technologic standard has been also presented and it also can be referenced by SIT and SITH. With the variation of the channel size and gate biasing, the SIT should exhibit a gradual transition from pentode-like to triode-like characteristic or conversely. During the transition of the I—V characteristics, the SIT will exhibit all type of the I-V characteristics: the good saturated pentode-like type, the poor saturated and with a tendency towards tribde behavior type, the mixed triode-pentode type, the triode-like type and the triode-like type however with a shifted certain voltage alongdrain voltage V_D axis. Based on the theoretical analysis and practical studies, some tables of parameter adjustment have been summarized and presented. For the typical mixed I—V characteristics, the technologic processes of diffused source region buried-gate SIT have been presented. For the buried-gate SIT, the best matching condition of epitaxy and lightly phosphorus diffusion has been searched out. Furthermore the epitaxy process has been stabilized and the problem of the inversion epitaxial-layer forming has been solved. The self-doping phenomena are examined.The importance of mesa and trenches etching are researched. The etching depth of partition trench, mesa and the gate electrode window are different from each other. It is conveniently that the three trenches can be etched simultaneously because of the smart design of three trench-layouts. Moreover, the supplemental boron diffusion of gate region has been cancelled. The volume ratio of etching solution is studied by etching test and the best etching processes are determined. Several measures against divergence and indeterminacy of technologic process are proposed.As the terminal shape of buried-gate SID, the necessity of the partition trench is argued. The static induction device is designed to be surrounded with the deep partition trench to cut off the various probable parasitical effects that may degrade the device performance, especially to avoid the parallel-current effect. A mathematical model for the parasitical effect of SIT is proposed and simulated with PSPICE. The simulation results are well agreed with the experiments. The seven field-limiting rings and one channel stopper have been applied to the diffused source region buried-gate SID. It is highly advantageous to improve blocking voltage.The new layout of LD-SIT-0703 is aimed at power SITH. The process flow is organized on the basis of BSIT. The normal I—V characteristics are obtained by experimental study. The break-over process is consulted. The expression of break-over voltage and current are provided. A new method has been proposed to work out the minority carrier lifetime at high level using the break-over characteristic.