Study Of Silicon Deep Reactive Ion Etching Process For MEMS Packaging

As the development of the Micro Electromechanical System (MEMS), the microstructures of MEMS devices also developed from simple surface structures to morecomplicated structures in three-dimensional forms, which will add complexities to thedevice fabrication. The fabrication of high aspect ratio structure is one of the mostimportant issues. The deep etching technology for silicon has been paid a lot ofattention to as one method of fabricating high aspect ratio structures. Thetime-multiplexed alternating process, whose patent held by Inc. Robert Bosch, is usedin silicon deep etching. It can make high aspect ratio and selectivity. The RIE-ICPetching system can control the plasma density and the ions bombardment energyindependently. In addition, it has other advantages, such as fast etching rate, simplestructure, low cost, high process stability, and so on. The RIE-ICP etching systemoccupies the main market position. In this paper, a series of experiments and analysishave been performed to realize the fabrication of the through silicon via, includingbarrier layer patterning process experiments, barrier layer material selection andprocess parameter optimization of the RIE-ICP etching system.This paper includes four main sections as follows:1. Design and achieve barrier layer patterning parameters through experiments.Pattern is accurate transferred from mask to the barrier layer, ready for thesubsequent deep etching for silicon;2. By analyzing the etching principle, research the relationship between thesilicon deep etching parameters, surface characteristics and the processspecifications; laid a theoretical foundation for the follow-up of the processparameters to optimize;3. On the base of a lot of experiments, make sure the relationship between theetching rate and the silicon deep etching parameters. In addition, make sure thatutilizing the photo resist as the barrier layer material;4. Overall consideration of many parameters such as etch depth, etch rate, sidewallprofile, selectivity and scallop size, optimize silicon deep etching parameters. Weachieve a through silicon via that depth179μm，etch rate10μm/min, side wallprofile90.9°, selectivity147:1, scallop size126.6nm finally.