Study Of Device Design And Key Process For E-mode GaN HEMT

With the advantages of high breakdown voltage,high switching frequency,and low on-resistance,AlGaN/Ga N HEMT devices are becoming more and more popular in the market,especially in the 650V consumer electronics market segment.However,AlGaN/Ga N HEMT devices are naturally depletion(normally open)type devices,and the threshold voltage of depletion type devices is negative,which can pose a great challenge to the complexity and safety of the circuit,so it is necessary to investigate how to realize enhanced(normally closed)AlGaN/Ga N HEMT devices with positive threshold voltage.In addition,the AlGaN/Ga N HEMT device preparation process also has some urgent problems to be solved,such as Ga N epitaxial wafer defect density,low resistivity without gold ohmic contact is difficult to prepare,Ga N material low damage etching,etc.,in which the Ga N material dry etching process is the focus of this thesis to research the problem.Therefore,the simulation and process research of enhanced Ga N HEMT devices are of great value and significance.The thesis adopts the method of p-Ga N gate cap layer to enhance the device threshold voltage,and the structural design and key processes of the enhanced Ga N HEMT power devices are studied in depth,and the main results achieved are as follows.(1)To achieve a device breakdown voltage of 650V and a threshold voltage of 1.5V,the thesis designs a metal gate field plate and a source field plate on the basis of a typical p-Ga N gate structure Ga N HEMT device.The thesis uses Silvaco TCAD simulation software to model and simulate p-Ga N gate Ga N HEMT devices with field plate structure.According to the simulation results,analyze the effects of various parameters on the device performance,including the effective doping concentration of Mg element in the p-Ga N gate,the thickness of the p-Ga N layer,the thickness of the AlGaN barrier layer,the Al composition in the barrier layer,and the gate-to-drain spacing The length of the metal grid field plate and the source field plate,especially the influence of the gate and source field plate on the device withstand voltage has been studied in detail.The simulation results show that the effective doping concentration of Mg element and the thickness of p-Ga N have no significant effect on the threshold voltage,and the saturated drain current density is directly proportional to the effective doping concentration of Mg and inversely proportional to the thickness of the layer.The Al composition and thickness of the AlGaN barrier layer are inversely proportional to the threshold voltage,and proportional to the saturation drain current density.The larger the gate-to-drain spacing,the breakdown voltage will increase and tend to be saturated.The metal gate field plate and the source field plate have a greater increase in breakdown voltage,and the metal gate field plate in the 4?m gate-drain device has a 22.1%increase in the breakdown voltage of the device.As the length of the source field plate increases,the breakdown voltage will increase.Big and tends to be saturated.The threshold voltage of the optimized Ga N HEMT device with gate field plate and source field plate after optimization can reach positive 1.5V,and the off-state breakdown voltage is 935V,which meets the design goals.(2)Based on the simulation results,p-Ga N gate Ga N HEMT epitaxial wafers with suitable epitaxial layer parameters are selected,and the p-Ga N gate Ga N HEMT devices are studied and prepared by combining the existing process conditions.The thesis designed 4 different gate field plate lengths,8 different gate drain spacings,and11 different source field plate lengths,and successfully prepared 23 p-Ga N gate Ga N HEMT devices.The actual test results show that the threshold voltage of the devices is 1.5V,and the threshold voltage of some devices is close to 2V,the minimum R_ON is 24.5?/mm,and the breakdown voltage of the devices is greater than 650V,and some devices are close to750V,which meet the design requirements.Meanwhile,the breakdown voltage trends of devices with different field plate structures and gate-drain spacing are consistent with the simulation results.Then,the gate leakage currents of different devices were studied,and it was found that the good or bad p-Ga N gate etching process is the key to the gate leakage current level size.(3)Based on the electrical property test and SEM test results,the thesis investigates the dry etching process of p-Ga N gate and proposes a method of fast ICP(Inductive Coupled Plasma)etching followed by slow ALE(Atomic Layer Etching)etching.The thesis optimizes the design of ICP fast etching process,including upper electrode power,lower electrode power,and Ar gas volume flow rate;the paper optimizes the design of ALE slow etching,including Cl₂/BCl₃ gas ratio in chemical modification,chemical modification time,physical etching cavity pressure,and physical etching time;based on the above design,the thesis combines the two process methods and performs etching process verification.The experimental study found that the optimized process can achieve an etching angle of 80?85°,a root mean square roughness of 0.447 nm,and a smoother etched sidewall without the presence of microgrooves,which is a significant improvement compared to the conventional ICP process widely used in Ga N etching field before.