Architecture Research And Design For The Key Units Of AVS Video Codec Chip

In the 1990's, digital video technology was widely used in the field of communication, computer, TV broadcast and so on. The related applications of digital video technology, such as TV conference, videophone, digital TV and media storage, have pushed the production of the first generation source coding standards, such as MPEG-2. In the new century, depending on the improvement of audio-visual coding technique and the enhancement of integration degree and processing speed of VLSI implementation, source coding standards get the best chance of being upgraded. Under these conditions, the second generation and high efficient source coding standards are emerging, such as H.264/AVC and AVS standard. H.264/AVC is an advanced video coding standard, which is developed by Joint Video Team of ITU and ISO/MPEG. AVS standard is a source coding standard of China with independent intellectual properties, whose applications are mainly SDTV and HDTV. For SDTV and HDTV sequences, the coding efficiency of AVS video standard is similar to that of H.264/AVC, and is about 2 or 3 times of that of MPEG-2.AVS video standard has been approved as Chinese national standard in Feb. 2006. Now the new standard is at the stage of industrialization. In the industrial chain of AVS standard, the research and design for AVS SDTV and/or HDTV codec chip is one of the most important parts. The architectures of three key units in AVS SDTV and/or HDTV codec chip, which is motion estimation unit, loop filter and variable length decoder, are carefully studied and discussed in this dissertation. The brief descriptions of these architectures are as follows.1. Motion estimation is a key unit of AVS video encoder chip, which takes about 60%~90% computational load of the whole encoder. Especially, AVS video standard adopts some new features such as multiple-reference-frames motion estimation, variable-block-size motion estimation, and high efficient coding modes for B pictures. Although these new features improve the coding efficiency, the computational complexity is greatly increased. Based on the idea of algorithmic and architectural co-design, one hardware-oriented fast integer motion estimation algorithm and its VLSI implementation are proposed in this...