Research On Study On The Dynamically Reconfigurable Array Co-porcessor

With the development of all kinds of programmable device techniques since 1980s, reconfiguration theory based reconfigurable computing becomes a central issue in the international research field. Reconfigurable computer based on the concept of reconfigurable computing is at the top in the high-performance computer field.After twenty years' research, the industry has agreed that the reconfigurable hardware can be embedded in the computer (or SOC) as the co-processor is the important characteristic of the high-performance computer (or SOC) in the future. Meanwhile the reconfigurable hardware structure has become the focus in the reconfigurable computer research.Now two main branches on next-generation reconfigurable co-processor is array-parallel mode and pipeline mode separately. Both of these two techniques are based on some similar array of reconfigurable cell, however, the technique with combining these two structures into one design has not been presented yet. The author designed a kind of Dynamically Reconfigurable Array Coprocessor (DReAC) with the combination of these two kinds of structures. This paper is the first research on them. The author presents the reconfigurable mode and the reconfiguration array optimization, and the application of DReAC.The structure model and the behavior model are presented and the whole reconfigurable co-processor is setup on these two models. This provides the research platform in this dissertation.DReAC co-processor's main structure is presented: the effective integration of globe management module, the reconfigurable unit and the reconfigurable computing array. Then the author setup a set of independent two-stage reconfiguration management mechanism. This realizes the MIMD (Multiple Instruction Multiple Data) data processing ability and many kinds of reconfiguration implementations of the DReAC.The author designed the function of global management module and defined the format of control instruction.The logic function selection and optimization procedure of the reconfigurable processing unit are discussed.The configuration instruction format of the reconfigurable processing unit are also defined, the topology selection and its optimization of the reconfigurable computing array inner interconnect network are discussed.The two-dimensional mesh structure model is setup and used in the application of the array utilization under the condition of different delays, which provides the experimental data for the exploration of the parameter-optimized reconfiguration array design.At the same time, the application of DReAC co-processor is discussed.