Programmable Logic Core Territory Automatically Generated Methods Of Research

Embedding programmable logic into SOC design will benefit SOC vendors in many fields as reducing development risks, shortening time-to-markets and prolonging the life cycles of SOC products. SOC with embedded programmable core is also called SOPC. Usually programmable cores will be shipped to SOC designers in the form of layouts. This embedding methodology demands programmable core's layouts fully meet the logical and physical requirments of SOC designs, which varies from system to system. Automations for programmable core's design based on SOC design requirments will greatly reduce the difficulties in SOPC development and shorten the design cycle as well.A programmable core generator is proposed in the thesis, which starts from a structual description and results in the layout of the programmable core. The generated programmable core contains logic block arrays of 4 inputs LUT and routing resources containing connection boxes of full connectivity and switch boxed based on unversal structure. This generator is capable of generating programmable cores of non-uniform routing architecture. The resulted layout can have differenc W/L ratios. The generator firstly obtains a netlist of programmable core by synthesis of the structual description. Then fioorplanning of the netlist is performed to meet given area constraints. Finally, routing of the netlist is done by existing EDA softwares to form up a complete programmable core's layout. An interface for embedding the generated programmable core into SOPC design is also provied by the generator.Programmable core specific synthesis and floorplan method are proposed in this thesis. The synthesis is achieved by creating connection boxes and switch boxes according to the routing channel width given in the structural description. The floorplan method is a tile-based one. The floorplan of each tile is achieved by an O-tree based floorplanning algorithms, which are put together to form up a complete floorplan of programmable core. Floorplans of adjacent tiles can joint seamlessly by introducing boundry obstacles into floorplan problem.Two design examples are also given in this thesis, which contains uniform and non-uniform routing architectures respectively. The generated layout is roughly 3...