CMOS Implementation Of WLAN Transceiver RF Front-End

Research on CMOS implementation of WLAN transceiver RF front-end is done in this thesis. The transceiver uses the most used super-heterodyne architecture, its RF front-end consists of low noise amplifier, down-converter, up-converter, preamplifier, LO buffer and PLL frequency synthesizer. The specifications for the transceiver RF front-end are deduced from IEEE 802.11b standard. Then, The RF front-end is implemented in CMOS process under the conditions of high integrity, low power and some design margin left. The research on the on-chip spiral inductors using passive component simulator, ASITIC, is done at first since the on-chip spiral inductors have a significant effect on the performance of the RF circuits. According to the research results, the design guidelines for the on-chip spiral inductors are summarized.The transceiver RF front-end uses the 1.8V power supply. In the design of the RF front-end, the effect of the low voltage power supply must be considered since the low voltage power supply limits the voltage swing of the circuit nodes and may affect the DC operation point, power gain and linearity of the RF front-end. The improved, suitable biased RF circuits are proposed to keep the excellent performance of the RF front-end even with low voltage power supply. The on-chip impedance matching is implemented in RF front-end, which simplifies the complexity of WLAN systems and reduces the cost. Moreover, in the down-converter the on-chip biased loop is used, which could improve the symmetry and linearity of the down-converter.The voltage-controlled oscillator and the dual-modulus prescaler are the most crucial blocks in the PLL frequency synthesizer. Two kinds of voltage-controlled oscillator (the quadrature voltage-controlled oscillator based on symmetrical spiral inductors and differential varactors, and the voltage-controlled oscillator with wide tuning range based on MOS varactors) and two kinds of prescaler (the prescaler using phase-switching techniques, and the prescaler using dynamic circuit techniques) are proposed. Then, the complete PLL frequency synthesizer is implemented, in whichthe voltage-controlled oscillator, dual-modulus prescaler, PFD, charge-pump, three digital counters, some digital registers, control logic and serial interface with the base-band processor are integrated.The WLAN transceiver RF front-end and PLL frequency synthesizer are implemented in TSMC 0.18um and 0.25um CMOS process, respectively. The measured results show the transceiver RF front-end and PLL frequency synthesizer satisfy the specifications of IEEE 802.11b standard, and could be applied to WLAN systems.