Research On The Realization Of The Channel Receiving Chip In Cable DTV

The digital television (DTV) will finally replace the analog television to become a new information industry, and it will eventually raise a new high economic tide. Some developed countries have studied DTV for many years and have formed some standard systems. To protect both the market and the economic benefit, it's greatly necessary to hold ourselves' DTV standard, and it's especially important that we could design and produce the critical IC chips for our standard when our standard issued.This paper mainly focuses on the research and realization of the channel receiving chip according with the DTV transmission draft in cable which we proposed. Certainly IC design involves many aspects, this paper only covers the theory, algorithm, architecture and design philosophy of the chip. It starts from the analysis of the theory and algorithm, then it presents the system architecture and some strategies used to realize chip hardware/software co-design, moreover this paper analyzes the design for testability (DFT) of the chip, finally goes deep into the study of the verification method and its role in the whole design flow of the chip. The chip referred by this paper has been successfully fabricated by 0.18um technology just one time, and it has been experimentally demonstrated at the "2002 Hangzhou Xihu Expo" with great success. It is proved that research in this paper is valid and efficient. This chip is one of the greatest scale system chips which are designed all by ourselves independently to possess of the independent intelligent property up to now. Its performance has achieved the international advanced level.In the first chapter, the history and the present situation of the DTV system is presented. The present DTV transmission system standards are given first, after that the DTV transmission draft we proposed is introduced compactly. And then, the design method of the IC is simply analyzed which is the basic of the deeper research of the chip.In the second chapter, the theory of VSB is described. Following that, the theory and algorithms of the main functional receiving components for our transmission draft are described in detail and analyzed deeply. These algorithms are applied in the chip successfully.The third chapter analyzes the process of translating the system performance to the system architecture based on the hierarchy design flow, and then, presents the method and the result of the system partition from different views such as: the oppositely absolute processing modules, convergent controllability, the simple and similar interfaces. Then the system architecture is further optimized by ways like: the normal and test data interfaces, control bus, configurable design based on I2C, using simplified EMCU. All the optimizations improve the suitability, scalability, flexibility and maintainability of the whole system architecture. Furthermore, this chapter analyzes the method and critical technique of the hardware/software co-design in general system and some concrete applications in this chip. Finally the design of RS decoder in this chip is described as an example of the hardware/software co-design based on ASIP, the construction and application of ASIP is also analyzed.The fourth chapter introduces the design flow using EDA tools based on standard cell, then it presents the DFT of this chip in detail which uses following techniques: full scan, BIST and boundary scan to improve the fault coverage. It presents the verification strategy used in the whole EDA design flow of the chip. The simulation on module level (inc. post-layout) uses the software event-driven simulator, the simulation of the associated modules or whole system uses cycle-basedsimulator and hardware emulator, For the gate-level netlist produced by using top-down design flow, the STA tool can analyze the static timing, and more formal verification is used to ensure the correct function. Moreover, a flexible, convenient and perfect test bench is proposed to enhance the verification process. Because of such rigorous verific...