Low Power Logic Circuits Design And Application In Risc Design

With the coming of VLSFs Sub-micron era, Low-power technique has been a growing demand in VLSI design. This thesis is an investigation into the logic circuit low-power design, embedded RISC core design and its low-power research.Flip-flops are the basic units in digital circuit. Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock. Then this principle is adopted in ternary circuit, a new ternary D type edge-triggered flip-fiop based on CMOS transmission gate is proposed. From the concept of triditional master-slave flip-flop, we propose a simplified positive edge-triggered flip-flop and prove the traditional positive edge-triggered flip-flop is the master-slave flip-flop designed based on basic flip-flop with single-rail input.According to the redundancy in digital circuits, we investigate the diversified redundancy-restraining techniques for lower-power CMOS circuits. To erase the redundant transition of the clock, the logic design of double-edge-triggered flip-flop is presented and applied in sequential circuit design. To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi-code assignment using redundant state is adanced to reduce power dissipation.Superscalar RISC microprocessor is the further development of reduced instruction set computer, it improve the instruction-level-parallism by means of adding parallel pipelining function units and dynamic on-chip scheduling. This thesis anslysises the architecture and the diversified techniques of superscalar computer. A novel 32 bit embedded fix-point superscalar RISC core is developed. Then we analysis the power dissipation of RISC core from view of instruction-set-architecture, datapath, supply voltage and dynamic power optimization.