Reserch And Design For The Low Power Dual Interface CPU Smart Card Chip

Currently smart card can be categorized into two major types:logic encrypt card and CPU card. The most common IC card in civil market is logic encrypt card. The type of IC card is very welcome to the customers due to its high performance price ratio, and it is widely used in public transportation, medicine, one card on campus, entrance guard and so on. But the logic card uses the stream encryption method and its secret key is very short, it can be cracked by hacks easily. The application areas such as finance, identify certified, electronic passport choose the CPU smart cards instead of logic cards.CPU card chip has dual security mechanisms. One is the chip itself integrates the encryption algorithm module, the other is its specific COS (Chip Operation System). Though the CPU card can indeed realize multi-application, its design is more complex than the normal logic card chip, without saying the dual-interface CPU smart card chip. Many research and development institutions are focusing on exploiting the chip design. The paper makes lots of research to realize the effective low power design for this smart card chip.Firstly, the paper describes the special low power requirement and challenge by the contactless application and presents nine effecitive low power design methods to lower the average power and peak power for both of contactless and contact applications from architecture level, circuit structure level and software/hardware combination level.The paper presents a creative method to automatically adjust the working frequency according to smart card real operation load for the first time, we call it as DFS (Dynamic Frequency Scaling) method which is specially used for the passive devices. The test result shows that the longest communication distance is improved from 6cm to 8 cm compared to the same smart card chip using the fixed frequency divided by 4 and the transaction time is saved by 18% in average, compared to the same chip using the fixed frequency divided by 8.The paper introduces the asynchronous circuits design method in detail. By using balsa language and Verilog languae, we realize the DES asynchrous circuit design based on the four-phase bundled-data protocol. The test results confirm the rightness of the asynchronous design method and its superiority in the low power design for the smart card.Finally, the paper gives the test result of the real chip and compares the transcation time among calculation, simulation and test results. It shows the chip has good performance for both of the transaction time and the communication distance in contactless application.