Research On Techniuques For Microprocessor Cache Access Behavior Analysis

The"memory wall problem has been a serious obstacle to the development ofhigh performance microprocessors for a long time In the multi-core era,the speedgap between computation and memory access is enlarged quickly since the incre-ment of the offCchip memory bandwidth is much slower than that of the number ofprocessor cores Consequently．the"memory wall"problem is getting deterioratedUnder such circumstances,the efficiency of the on-chip memory system becomesthe key to the performance of a multi-core system Therefore,in the multi-core era,the on-chip memory system must be optimized as much as possible to mitigate theharmful effect of the"memory wall"problemThe rise of the multi--core architecture means both challenges and opportuni--ties to on-chip memory system optimization On the one hand,both the last levelcache and offCchip memory bandwidth are usually shared among all processor coresin a multi-core processor This sharing．due to resource contention among processorcores,will lead to the degradation of overall performance,fairness and quality of ser-vice On the other hand．plenty of transistor resources are available in a multi-corechip,which means multiple policies can be implemented simultaneously from whichone policy can be chosen that matches the behavior of the currently running applica-tion the best This kind of"application behavior specific optimization''can raise theefficiency of the on-chip memory system to a new level However．a prerequisite toeither resource contention mitigation methods or application specific optimizationsis the deep understanding of the cache access behaviors of programs Therefore,cache access behavior analysis is fundamental to the solution of the"memory wall"problem in the multi-core eraThis paper thoroughly studied the cache access behavior analysis techniquesfrom the methodology and the model perspectives,respectively The main contri-butions are as follows:1 A dynamic binary translation(DBT)based program behavior analysis ac- celeration technique is proposed Program behavior is traditionally analyzed through simulation,which is quite inefficient This paper studies the prob- lems related to program behavior analysis through DBT technique A general framework of DBT based basic block vector(BBV)profiling,DBT-BBV,is proposed Several of its key design choices are discussed and evaluated Two optimization methods is proposed to reduce the BBV profiling overhead One counter compensation method is proposed to improve accuracy A highly ef- ficient BBV profiler,QPoint,is implemented based on the DBT-BBV frame- work and the proposed efficiency-and accuracy-enhancing techniques Exper- imental results show that the performance of QPoint is l 0 5 times of that of a functional simulator based BBV profiler．and l 73 times of that of a simple implementation2 A method is proposed to improve the accuracy of the SimPoint based program behavior analysis technique In SimPoint based program behavior analysis,if the same simulator is used for both BBV profiling and detailed simula- tion,then the simulation points generated by BBV profiling can be used to guide the detailed simulation accurately Unfortunately,when BBV profiling is carried out through DBT technique,the execution traces differs quite a lot between the BBV profiling execution and the detailed simulation execution of the program,which makes the simulation points obtained by DBT tech- nique inaccurate for guiding detailed simulation This paper shows that if not handled appropriately,the difference of the execution trace may cause serious accuracy problems to the simulation results A program execution trace model is proposed to determine various factors that may affect program execution trace,and several methods are proposed to eliminate these factors'influence Experimental results show that the proposed methods can effectively elimi- nate the errors caused by DBT based BBV profiling Experimental results show that the proposed methods can eliminate the execution trace difference of 23 out of 28 SPEC2006 benchmarks The execution differences of the other 5 SPEC2006 benchmarks are also very small,and are negligible3 An accurate model is proposed for estimating SDH(stack distance histogram) from TDH(time distance histogram)Through in-depth analysis of the prop- erties of time distance,this paper discovers a constraint that is inherent to time distance series:the"shadowing"effect This effect can seriously affect the accuracy of the TDH based cache access behavior analysis models By studying the property of the"shadowing"effect and its impact on present cache models,this paper proposes the SASS(Shadowing aware STATSTACK model)model,which is an improvement over the STATSTACK model Ex- perimental results show that by taking into account the"shadowing"effect．the SASS model can improve the SDH estimation accuracy effectively and iS the most accurate SDH estimation model when evaluated with SPEC2006 benchmarks4 A method fOr ideal address trace synthesis from arbitrary data reuse patterns is proposed Ideal address traces with various data reuse patterns are impor- tant tools fOr cache access behavior model construction and evaluation This paper proposes methods fOr ideal address trace synthesis from either SDH or TDH Although synthesis algorithm fOr SDH is straightforward．synthesis al- gorithm fOr TDH must take into account the"shadowing"effect Otherwise．the synthesized address traces would be wrong This paper proposes two ideas,probability transformation and probability compensation,to accommo- date the"shadowing"effect in ideal address trace synthesis Experimental results show that the proposed algorithms can efficiently synthesize ideal ad- dress traces with arbitrary data reuse patterns...