Way-predict Based Low Power Cache Design

As the mobile devices, such as smart mobile phone and panel computer become prevalent, low power has become an essential for the micro processor. And as one of the main sources of the processor, cache is also eager for low power design. This thesis proposed three kinds of low power design technology based on way predict, which could reduce the access power of cache, adding little resources, with little performance degration. The researched contents and original contributions of this thesis are as follows:1. Instruction based classified way predict for cache. On the base of researching on the relation between different kinds of instructions and different sources of predicted ways, classify the instructions according to the sources of predicted ways. And using the instruction information from different stages of the processor pipeline, choose the needed predicted way. Then the instruction composition in procedure is researched on, to decrease more power, with less dditional resources and performance loss. And the relation between predicting resources, predicting efficiency, power reduction and performance loss is analyzed, to get the best configuration. This technology can significantly reduce the power, but the additional resources and the performance loss are a little big.2. Loop based single trace way predict for cache. According to the property of the history based prediction, analyze the defect of classified way predict, and propose single trace way predict. The scheme uses loops as the premise of using way predict. The way predict will be used only when encounter a loop and this loop is recorded. Then analyze the relation between resources allocation and predicting efficiency in this scheme. The experiment results show the scheme can significantly reduce power, without much additional resources and performance loss.3. Loop based multiple trace way predict for cache. By using multiple traces in one loop, solve the trace collisions raised by branch instructions. Analyze the amounts of loops and branch instructions and propose the best amount of traces. Multiple trace way predict is better than single trace way predict, especially the reduction of performance loss, when they have same and enough resources.