Analitical Modeling The Downstream Cache Behaviors Based On Software Memory Accessing Traces

In the design of modern CPU,to mitigate the speed gap between CPU and main memory,multi-level cachesare widely utilized.Therefore,the evaluations of the performance of downstream caches become more and more important.In this thesis,we proposed one analytical model,which can fast evaluate the miss rate of the downstream Cache.Because cycle-accurate simulation of L1 Cache is not needed in this model,it improves the evaluation efficiency of memory subsystem.This thesis proposed two new metrics to describe the characteristics of the software---Reuse-distance-Stack-distance-Transfer(RST)table and reuse epoch hit/miss histogram(Hit RDH).RST can be used to describe the relationship between reuse distance and stack distance;Hit RDH is used to describe that in a reuse epoch with certain reference distance,how many references hit/miss.Based on these two metrics,we build the analytical model to predict the distance histogram of downstream caches.In addition,with the help of Stat Stack and Stat Cache,our model can predict the miss rate of the L2 Cache;with the help of Stat CC,our model merges the distance histograms from L1 DCachhe and L1 ICache to take the effect of ICache into consideration.In our experiments,we use 15 benchmarks from SPEC CPU 2006 and 9 benchmarks from SPEC CPU2017.Compared to the results from cycle-accurate Gem5 simulations,the maximum absolute error of predicted miss rate is 9% with the average error of 4%.Because the profiled information can be reused when the L1 Cache configuration does not change and L2 Cache configuration changes,the average evaluation time is decreased.The evaluation time can be sped up almost 30 X.