Multi-Path Trace Processors

According to estimation, semiconductor technology will continue the development progress in the future. It is determined that huge amounts of transistors will be integrated on a chip. How to make these huge amounts of transistors to higher performance remains a big challenge.Speculative execution is a way to higher performance. This dissertation analyzes the insufficiency of speculative mechanisms in advanced processor implementation. In a long-pipeline machine, speculative execution increases misspeculation penalties, and makes processors much complex. To deal with the insufficiency of speculative execution, we propose Multi-path trace processors (MPTP).In MPTP, branches with less predictability will execute both directions to minimize misprediction penalties, while branches with high predictability will execute only the predicted path to expand instruction window. Based on trace processors, MPTP duplicates multiple superscalar processors as processing elements (PE), and executes instruction traces in PEs.This dissertation illustrates the principles, structures and control mechanisms of MPTP in details. We make evaluation of MPTP model by simulation. The key technology of MPTP includes:First, multi-path execution based on branch predictability mechanism (MPEBP) is proposed. MPEBP mechanism evaluates branch prediction confidence, and the evaluation output determines branch execution behavior. A different confidence threshold will affect path divergence and resources usage. We study the relationship between confidence threshold and the coverage of misprediction branches by simulation.Second, trace preconstruction based on branch target profiling mechanism (TPBTP) is proposed. TPBTP mechanism evaluates branch target from a direct branch in advance, so to make up the insufficiency of branch predictor and branch target buffer, and constructs instruction traces before program execution.Third, multiple paths control mechanism is developed. Multi-path execution is controlled through trace identifier, which is generated by coding branch directions in a path. Trace identifier benefits propagation of data and control within multiple traces.Fourth, speculative trace execution mechanism is developed. Trace execution exploits control independence. Coarse grain independence incorporating with fine grain independence leads to hierarchical instruction window, which reduces instruction window complexity.We use SimpleScalar simulator, which is developed by University of Wisconsin-Madison, to evaluate our model. SimpleScalar is a well-known micro-architecture simulator. We rewrote it to fit our design. SPECint95 benchmark suite is used to validate MPTP.With restricted resources, our simulation indicates that MPEBP mechanism has well covered most of the mispredicted branches, and TPBTP can improve instruction fetch rate efficiently. Taking one with another, the MPTP model is a good candidate for implementing next generation microarchitecture.This dissertation makes two main contributions: First, a novel processor microarchitecture MPTP is fully developed. Second, performance evaluation of MPTP is studied.