Task Scheduling Algorithm Based On Reconfigurable Cell Array

Reconfigurable Computing System has high performance, high speed, as Application Specific Integrated Circuit (ASIC), and has general purpose nature and programmable nature as Reduced Instruction Set Computer (RISC). However, the main drawback for Reconfigurable Computing System to have a broad application prospect is that the time consumed for context words transferring and data transferring between Reduced Instruction Set Computer and Reconfigurable Computing System is so long that the performance of Reconfigurable Computing System decreases, so how to improve the performance by task scheduling has been a hot research issue.A dynamic list scheduling algorithm based on the architecture of Reconfigurable Computing System that has multiple reconfigurable computing arrays is proposed. This dynamic list scheduling algorithm uses a new task priority algorithm that can get efficient use of the parallel nature among the tasks to schedule: overlapping the computing time of one reconfigurable computing array with the configuration time and data transferring time of other arrays.In order to check whether the Reconfigurable Computing System can achieve a better performance with the proposed dynamic list scheduling algorithm, a new architecture of Reconfigurable Computing System is built. The whole system includes Reduced Instruction Set Computer, memory, bus and reconfigurable computing arrays, and the compiler based on the research before is improved. Compiling the C code with this new compiler, the new C code and the new architecture of Reconfigurable Computing System co-simulate on the platform of SOCdesigner. For IDCT, FFT and 4?4 MATRIX MULTIPLY, because the computing time overlaps parts of configuration time and data transferring time, this new architecture of Reconfigurable Computing System with the new dynamic list scheduling algorithm has an average of 10% speed up compared with the old Reconfigurable Cell Array.In order to get the real performance, the reconfigurable computing array is implemented in RTL level and synthesized. The front-end synthesis of array using SMIC 180nm process shows that the frequency can achieve as high as 100MHZ.