Research On Techniques Of Soft Error Analysis And Mitigation In Nanometer Scale Integrated Circuits

With the technology scaling, the microelectronic manufacturing process has entered nanometer era. Because of its excellent performance and low power consumption, nanometer scale integrated circuits have been widely used in electronic communications, computer, aerospace, military and consumer electronics devices. On the other hand, due to the great reduction in supply, increasing frequency, continuous decreasing of node capacitances and the rapid growing of chip complexity, nanometer scale integrated circuits become more and more sensitive to the environment. When hit by high-energy particles or interfered by external noise, the nano-integrated circuits'internal state can be destroyed and this can further lead to the circuit error. Since this type of error is transient, random and recoverable, it is called"Soft Error".In nanometer technology, soft errors are the mainly reason for integrated circuits failure. Frequent occurrences of soft errors will lead to an unstable system and seriously affect the reliability of integrated circuits. To make things worse, soft error becomes more and more seriously as the technology scales down and can cause many problems, such as date corruption, execution error, and even system crash in the worst case. So it should be paid to enough attention, especially in the cases of aviation, aerospace and military which demands high reliability because of their poor environment. Nowadays, soft error becomes one of the most serious challenges which require particularly consideration.This thesis mainly studies techniques of soft error analysis and mitigation in nanometer scale integrated circuits. This study primarily focuses on units or structures which are difficult or costly to protect and have a significant influence on the system soft error rate. The purpose of this thesis is not to completely eliminate soft errors in nanometer scale integrated circuits, but to develop a lower cost mitigation technique and enhance the system's reliability, and to emphasize high efficiency and low overheads. The innovations of this thesis are as follows:1. Soft error analysis and mitigation techniques of content addressable memories (CAM). In the integrated circuits, CAM is one of the most sensitive units to soft errors, but the traditional fault-tolerant technique, such as error-correcting coding techniques, can't apply to it due to its special structure. To address the problem, after analyzing soft error mechanism and profile of CAMs, this thesis introduces a method that uses stable structure to enhance CAM cells. Furthermore, this thesis also introduces two reliable CAM cells and a soft error protection mechanism. The two structures, Dual Cell Feedback Reliable CAM and Dual Cell Keeping Reliable CAM, are based on dual cell redundancy. The mechanism called Ignore Mechanism is an fault protection scheme based on dual cell CAM structure. Due to the limitation of the CAM cell hardening, this thesis proposed a simple but effective soft error tolerant structure which is based on the triple-value match line and can detect any one bit error in the CAM. Experiment results show that the proposed techniques can effectively mitigate the soft error problem at the cost of very low overheads.2. Cost effective soft error mitigation techniques of sequential circuits. Sequential circuits are an important component of the integrated circuits. In the nano-technology, the sequential circuit becomes very sensitive to soft errors. Although the traditional redundancy-based enhancing technique can migrate the soft error effectively, it brings considerable area overhead as well. This thesis firstly investigated the reliabilities of different register structures, and then designed a soft error immunity register, DMTS-DR. To mitigate the circuits'soft errors, a greedy-based sensitive register replacement algorithm is proposed. Its main idea is to replace the most sensitive registers with redundancy structures. Since the greedy algorithm is sometimes a sub-optimal solution, this thesis proposed another heuristic algorithm. Experimental results prove that the proposed techniques achieve a good trade-off between reliability and area overhead.3. Soft error analysis and vulnerability optimization techniques of dynamic circuits. Dynamic circuits, owing to its outstanding performance, are widely used in high-speed circuit design. However, dynamic circuits are very sensitive to soft errors, and this severely limits its application. This thesis analyzes the soft error sensitivity of dynamic circuits, and develops an critical charge analytical model for some of the highest vulnerable cases. Due to the accurate analytical model is too complex to calculate, this thesis, by using an approximate method, finally present another simplified linear model which can be used both in the vulnerability analyzing and automatic CAD tools. Based on the analysis model above, five techniques are designed to mitigate soft error vulnerability of the dynamic circuits and each of them has been evaluated carefully. Experimental results demonstrate that the proposed model has high accuracy, and the optimization techniques can mitigate soft errors in dynamic circuits.4. Low overheads soft error mitigation technique for arithmetic units. Arithmetic unit is the most important component both in the microprocessors and integrated circuits, and its validity may directly affects the system's reliability. In nanometer technology, the soft errors in the arithmetic unit can't be ignored. Since the tradition mitigation technique's area overhead is too large, this thesis introduces the idea of exploiting the inherent redundancy resources to mitigate the soft errors. After investigating the inherent redundancy in the parallel adders, a soft error tolerant adder STPA was designed. An effective fault injection-based soft error estimation method is also proposed for the proposed adder. Experiments prove that the proposed structures sufficiently exploit the circuits'inherent reluctant resources and can effectively mitigate the soft errors problem of the arithmetic unit while only with small overheads. To summary, this thesis provides an effective solution for the soft error problems in the nanometer scale circuits, and further gives a theory and practicable foundation to improve the reliability of the nanometer scale circuits.