Research Into Reliability Of 550V Lateral IGBT On Thick SOI

The thick Silicon On Insulator (SOI) process owns good insulation effect, high radiation hardness capability and small parasitic parameters. Meanwhile, the Lateral Insulator Gate Bipolar Transistor (LIGBT) device has high breakdown voltage, large current capability and integratable advantages. Therefore, the SOI-LIGBT is an attractive device in the power Intergrated Circuits (ICs), and is widely used in the intelligent household applications, electric vehicle, industrial control, display drivers and son on. The SOI-LIGBT will be a nuclear device for power ICs. However, the LIGBT on thick SOI would face serious reliability problems due to the electrostatic strike from pins, the high operation voltage, the high current density, the self-heating effect and so on. The reliability problems prevents the applied range and the development of the corresponding ICs. The Electrostatic Discharge (ESD), Hot-Carrier Injection (HCI) and Latch-up are the most common reliability problems of LIGBT on thick SOI. Therefore, the three reliability problems are investigated in detail in the dissertation. The investigations provides theoretical supports and conferences for the reliability evaluation of the LIGBT on thick SOI and is significant for the reliability improvement. The main works and innovations are concluded as follows.1. The response characteristics of SOI-LIGBT under ESD condition are investigated, including gate coupled region, voltage snapback region and voltage hold region. The devices’failure mechanism under ESD condition are also revealed. Based on the theories investigations, we further build the ESD characheristic model, whose error is less than 10%. Moreover, a novel SOI-LIGBT structure with partially grounded gate is proposed. The structure can improve the ESD capability by 20%with a little current capability loss (5-10%).2. The HCI degradation mechanisms of SOI-LIGBT are extracted. The investigations find that the damage in the drift region has no impact on the device characteristics degradation. The worst HCI stress condition is the maximum gate voltage stress condition. The dominant degradation mechanism under worst stress condition is the hot electron injection and interface state generation in the channel region. The HCI degradation during the device turn-on and turn-off process is also investigated. Finally, the lifetime model of SOIO-LIGBT under dynamic stresses is build, whose error is less than 7%.3. Two SOI-LIGBT structures with improved HCI reliability is proposed. The structure with N+ring around the anode can decrease the HCI degradation by compromising the current capability. The structure with extra P-type region in the drift can effective improve the HCI reliability with the other device characteristics unchanged.4. The latch-up mechanism of SOI-LIGBT is investigated in detail. Based on the latch-up mechanism, the hole current in the SOI-LIGBT is modeled firstly, whose root-mean-square error and maximum relative error are less than 1% and 3%, respectively. Then, the latch-up voltage model is completed. The model considering the impact of temperature on latch-up dependent safe operation area.5. Two high latch-up reliability SOI-LIGBT structures are proposed. The structure with P-type buried layer can enhance the latch-up voltage by 60%, while the current capability loss is less than 10%. The structure with Trench grounded can improve the latch-up voltage by 25% with the other characteristics are maintained.