| Analog-to-digital converters(ADC) are indi spensable devices in the process converting analog signal to digital signal. High resolution ADCs match the requirement of high performance, and are in urgent need in the advanced digital audio signal processing system. The sigma-delta analog-to-digital converter(∑-Δ ADC) with the high resolution which the traditional Nyquist ADC(Nyquist-Rate ADC) can never achieve has become the only choice for the realization of the high resolution ADC. The ∑-Δ ADC achieve the high resolution with the use of oversampling and noise-shaping and down-sampling digital decimation filtering technologies. It reduce the difficulty of analog circuit design by processing low-resolution signal in analog domain, and it achieves high resolution changed with the speed with making full use of the powerful digital signal processing by processing high resolution signal. And the ∑-Δ ADC is easy-integrated, of superior overall performance and perfectly compatible with standard CMOS technology. With so much outstanding merits, the ∑-Δ ADC is the most popular problem and the main directions of the research of high resolution analog-to-digital converters. The sigma-delta modulator is the core and critical part of the ∑-Δ ADC, and the performance of the modulator directly determines the overall performance of the converter. And so the design of the ∑-Δ modulator is the difficulty and focus of achieving high resolution. Based on this reason, the paper starts the research of the high resolution ADC.First, through the systematic comparison of the performance and characteristics between Nyquist-rate ADCs and ∑-Δ ADCs, the outstanding advantage of the ∑-Δ ADC is fully demonstrated. Secondly, based on the discussion in detail of the key techniques and principles of the ∑-Δ modulator, the basic structure modulators’ characteristics of first-order, second-order, single loop higher-order, multi-stage and multi-bit quantization are analyzed and compared, and then the relationship of the performance of the modulator with the number of the order, the oversampling rate and the number of the quantization bits is summarized. Finally, the entire design methods and processes of the modulator are summarized and demonstrated in detail from the parameter determination, structure selection, system design, circuit implementation, to the layout planning and chip testing.By the deep study of the modulator system architectures, a complete design method of the systematic modulator is summarized through modeling and simulation in MATLAB software. This method comprises the following, determining the structure type, order, oversampling ratio, and number of quantization bits with the bandwidth, resolution and applications of the ∑-Δ modulator, designing the noise transfer function with poles and zeros optimized, selecting and optimizing the specific modulator structure to realize the noise transfer function, determining and optimizing the modulator structure’s coefficients(feedforward factors, feedback factors and integral gain factors) of by using SIMULINK, and testing the performance of the ideal modulator system architecture to find it is suitable for the design specifications or not through simulation. Using this system design methodology, the modulator structure with single-loop second-order 4-bit quantization and oversampling rate of 256 is determined and suitable for the design specification requirements of this article.The noise and non-idealities of the switched capacitor circuits will make influence on the performance of the ∑-Δ modulator which is made up of the switched-capacitor(Switched Capacitor, SC) circuits. The noise and non-idealities of the switched capacitor circuits are theoretically analyzed comprehensively, and the degree of impact on the modulator of some important factors is analyzed quantitatively through modeling and simulation in SIMULINK software. The performance requirements of each module obtained by systematic simulation provide the design basis the design of the module circuits of the ∑-Δ modulator. With the performance to guide the circuit design, the time of the circuit design cycle is shorten and the design efficiency is improved.A high resolution two-channel audio ∑-Δ modulator is designed in this paper, wherein each channel consists of an identical modulator which is the optimized modulator architecture obtained in the system design process, and the identical modulator is a single-loop second-order 4-bit quantization modulator with the cascade integrator feed backward(CIFB) structure, where the integrators are replaced by the delay integrators. The use of the single-loop second-order structure simplifies circuit design and improves the stability of the modulator, the adoption of 4-bit quantization improves the resolution and the stability of the modulator, the delay integrator integrator introduce error smaller than the zero delay integrator, the CIFB structure increases the stability and dynamic range of the modulator. The circuit of the single-channel modulator includes two switched capacitor integrators(each integrator includes operational amplifiers, switches and capacitors), a 4-bit form Flash ADC acting as the quantizer, a dynamic element matching(DEM) module realized with the clocked averaging algorithm(CLA) technology, two DACs achieved using switched capacitor array, and an encoder(Bin-to-Therm Encoder). In addition the entire two-channel ∑-Δ modulator system includes a bandgap reference circuit and a clock generation circuit sharing by each channel. The modulator circuit adopts a fully differential structure, which not only can eliminate even harmonics and improve the power supply voltage rejection ratio reduce the common mode noise of the circuit as well as other non-ideal factors, but also can effectively increase the input and output swing and improve the dynamic range.As high-performance operational amplifiers are needed by the high resolution D-S modulator, a dynamic frequency compensation two-stage high gain operational amplifier is designed in this paper. Of this operational amplifier, the first stage uses cascode NMOS input structure, and the second stage uses a common-source structure, the two-stage structure effectively improves the gain of the amplifier. In the operational amplifier, the dynamic RC(Resistor Capacitor,RC) frequency compensation is realized by a switched-capacitor in parallel with the compensation capacitor. In the sampling phase, the op amp phase margin is increased, which improves the modulator stability. In the integrating phase, the gain and slew rate of the op amp are improved, which can reduce the influence to the modulator by limited DC gain and slew rate. The pre-amplification latch comparators are adopted in the 4-bit flash ADC, which not only has the characteristics of high gain, high speed, high sensitivity, and low power consumption, but also can reduce the effect of kick back noise on the quantizer output.To reduce the impact of DAC nonlinearity on the performance of the modulator, the dynamic components matching(DEM) is made by using the clocked averaging algorithm(CLA) technology, which randomized the feedback path of the 16 outputs signals of the quantizer. Thereby the DAC nonlinearity error is reduced and the dynamic performance of the modulator is improved, and the power and area consumption of the modulator system increases marginally. The value of sampling capacitor, the integrating capacitor and the feedback capacitor is selected rationally, and these capacitors implemented with the use of cell capacitor array, which reduces switch noise while also reduces the consumption of power and area. High-performance bandgap reference sources are designed to provide accurate voltage and current reference for each module of the modulator circuit. Two-phase non-overlapping clock circuit provides the clock control signal of a well-designed timing for the integrators, quantizer and switched capacitor DACs.The two-channel high resolution audio multi-bit Σ-Δ modulator in this paper is designed with Chartered 0.5μm CMOS technology, and the whole layout area is 6 mm2. The operating voltage of the Modulator is 5 volts, and two-channel power dissipation is 168 m W. Operating frequency is 12.288 MHz, and the oversampling rate is 256, and the signal bandwidth is 24 k Hz. With-3d BFS @ 15 k Hz input signal, the modulator is simulated, and the SNDR reaches to120.9d B, and its effective number of bits is 19.8。...
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