Study On The Space-borne Solid State Recorder ——about Hardware Architecture

Space-borne Solid State Recorder(SSR), which is one of the most important components of integrated electronic systems, keeps a lot of in-orbit experiment data. The experiment data is the main output of space mission. With the rapid development of space astronomy technique, space exploration missions vary. Therefore, the demands for space-borne SSR are keeping increasing. This thesis analysis the related research at home and abroad from the five aspects: the chip medium, the capacity, the throughput, scalability and reliability. This paper focus on the research of key technologies following the trend of higher scalability, flexibility and reliability,The problems brought by enlarge the capacity and throughput is focused and solved with the working principle and work-flow. First problem is the lowing density of the storage area. The storage areas decline in storage density for using SRAM as the buffer, which limits the capacity extension of SSR. Replace SRAM with SDRAM can solve the problem, while it is difficult to control and whose throughput will impact the throughput of the whole SSR. An equation is proposed to rational control the buffer and the NAND FLASH to attain a higher apparent throughput. Second problem is the increasing pin counts. With the increasing of capacity, the pin counts also increase. More pin counts need more area and an ASIC with more resources, but most of which are unnecessary. An optimal connection method is proposed to solve it.Two fast start-up methods are designed for large scientific satellites and micro satellites respectively to improving flexibility of SSR. The low-cost method based on the reserved area is for the micro satellites. It divides the main store area of NAND FLASH into data area and reserved area. The reserved area is used to store Block Access Table(BAT). The more concentrated store method can reduce the start-up time. The reliability of BAT itself is reinforcing by a redundant copy. Using pipelining techniques to update of BAT reduces the updating time make the whole SSR more reliable. The method is applied in an actual task and the start-up time is just 0.1% of the traditional one when restarted by software while the start-up time is 0.2% of the traditional one when broke down. The large scientific satellites are designed to be long-life, so a method based on MRAM which is high speed, high density, small cell size, and almost unlimited endurance. The addition of MRAM in storage area make the FPGA manages BAT and NAND FLASH in parallel, so the update time is just about 35 ns which ensure that the BAT can get rid of the loss by power-down. Also the BAT is stored highly concentrated. Therefore the SSR start up more quickly.The basic performance of SSR would be improved significantly through the technologies mentioned above. Research on SSR architecture can further enhance the scalability and applicability. The development work of modern satellites has strict requirements on time, cost and quality. However, the traditional BAT is overstaffed and the software and hardware are tightly coupled, which leads to a low reusability. One structure with better reusability, modularization, integration and reliability is proposed. It can be adapt to the micro satellite through adjustment which makes the SSR smaller with lower power consumption and a higher capacity density.From the aspect of hardware, separating the component to functional module, separating the SSR internal and external interfaces, to unify both management bus and data interface. Interfaces connecting to the payloads are allocated to the Combiner from the SSR. The Combiner collects the data from payloads and transfers it to the SSR through a standard interface. CPCI bus is adopted as the management bus. The bus is flexible so that the SSR could change, adjust or expand the connection of the CPU and the FPGA. From the aspect of link, high speed serial data bus is used point to point to make sure the transmission stable, reliable and fast. The bus is serial but it’s both ends have a parallel communication through the bus’ s serial-parallel/parallel-serial conversion function. The bus is very fast and it wouldn’t slow down the maximum of SSR throughput speed. From the aspect of power supply, every functional module gets its power independently to improve the ability against single exception. From the aspect of FPGA design, one semi-autonomous management scheme is proposed. The FPGA design scheme is made to reduce the coupling degree of the software and hardware, reduce dependence to the interaction with management bus, and promote the hardware autonomy of storage management. The algorithm supports the extensible structure. The mathematical model calculation shows that semi-autonomous management algorithm is effective in reducing the time of write, read and erase operation, reducing the occupation time and the interrupt frequency of management bus.