Implement Of OR1200-based System-on-Chip And Conformable Verification Of LDPC

As the popularity of 4G communications and the future high-rate interaction of large volume information of 5G, requirements for information transmission accuracy and reliability on the mobile communication devices such as smart phones, tablet PCs, wearable device have to reach a higher level. Channel error correction code is the core of modern digital communication technology to ensure maximum reliability of information transmission.Besides, the low density parity check(LDPC) code is also an excellent channel coding to meet the needs of low error rate. Since the biggest advantage of mobile devices is its portability, which requires the device not only has a faster calculation speed but also has a smaller volume. With the development of integrated circuit and SoC technology, a function used to take a plurality of chips to realize can now be implemented by a SoC system. SoC is a complex integrated circuit whose software is based on embedded operating system and core of hardware is IP core reuse technology, it’s a chip but integrated the whole system.First a framework and its implementation of SoC chip system were proposed. A free open-source processor OpenRISC 1200 was selected as core device and Wishbone bus as bus standard. Other components of the SOC include timer, memory RAM, instruction/data caches and arbiter. Then, the design implemented and verified the basic SoC.Secondly, a verification platform with SystemVerilog was built to verify the LDPC decoder IP core which was designed by my schoolmate in the same group. The verification platform adopted the combination of random testing and directional testing. And then, the Wishbone standard bus interface was designed for the IP core, after that, the IP core was added to the SoC system as a independent IP core.Then,SoC system added with LDPC decoder IP core was verified. In order to facilitate subsequent FPGA download test, the baud rate was added to the validation process for 9600 UART serial interface IP unit, the LDPC decoding results were readed via a serial port. A Perl script was written for the proposes of comparing read out results with the expected results.The results show that read 4608 LDPC decoding data and expected values are exactly the same.At last the quickly FPGA verification process was proposed and the whole SoC system on model for Altera Stratix II EP2S60F1020C3 was successfully transplanted on the FPGA. Actual comprehensive frequency was up to 115 MHZ, using Combinational ALUTs was 7594, Logic registers was 3951 and theoccupancy rate of Block memory has reached 393/424(92.7%). Memory utilization reaches 92.7% because of LDPC decoder requires a lot of storage unit for iterative calculation. By means of verification of software and hardware, it demonstrates that the LDPC decoder as independent IP applied to the scheme is feasible and effective in SoC system.The main contribution of this thesis is to propose a method of applying channel codec module LDPC decoder which is an independent IP core to a complete SoC system and results of hardware and software co-verification show that the scheme is feasible. You would see a better solution to many technical difficulties occurs during process of hardware design and validation, such as the Wishbone bus sharing in coordination with the priority of each IP, FPGA transplant verification of SoC system and a plenty of debugging code and modules, etc.